Invention Grant
- Patent Title: Device topology for lateral power transistors with low common source inductance
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Application No.: US17117449Application Date: 2020-12-10
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Publication No.: US11515235B2Publication Date: 2022-11-29
- Inventor: Ahmad Mizan , Edward MacRobbie
- Applicant: GaN Systems Inc.
- Applicant Address: CA Ottawa
- Assignee: GaN Systems Inc.
- Current Assignee: GaN Systems Inc.
- Current Assignee Address: CA Ottawa
- Agency: Miltons IP/p.i.
- Main IPC: H01L23/482
- IPC: H01L23/482 ; H01L29/778 ; H01L29/20

Abstract:
Circuit-Under-Pad (CUP) device topologies for high-current lateral power switching devices are disclosed, in which the interconnect structure and pad placement are configured for reduced source and common source inductance. In an example topology for a power semiconductor device comprising a lateral GaN HEMT, the source bus runs across a centre of the active area, substantially centered between first and second extremities of source finger electrodes, with laterally extending tabs contacting the underlying source finger electrodes. The drain bus is spaced from the source bus and comprises laterally extending tabs contacting the underlying drain finger electrodes. The gate bus is centrally placed and runs adjacent the source bus. Preferably, the interconnect structure comprises a dedicated gate return bus to separate the gate drive loop from the power loop. Proposed CUP device structures provide for lower source and common source inductance and/or higher current carrying capability per unit device area.
Public/Granted literature
- US20220139810A1 DEVICE TOPOLOGY FOR LATERAL POWER TRANSISTORS WITH LOW COMMON SOURCE INDUCTANCE Public/Granted day:2022-05-05
Information query
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