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    Scalable circuit-under-pad device topologies for lateral GaN power transistors
    2.
    发明授权
    Scalable circuit-under-pad device topologies for lateral GaN power transistors 有权

    公开(公告)号：US11139373B2

    公开(公告)日：2021-10-05

    申请号：US16688008

    申请日：2019-11-19

    Applicant: GaN Systems Inc.

    Inventor： Ahmad Mizan ,  Hossein Mousavian ,  Xiaodong Cui

    IPC: H01L29/06 ,  H01L23/482 ,  H01L23/528 ,  H01L23/522 ,  H01L29/205 ,  H01L29/423 ,  H01L29/20 ,  H01L29/417 ,  H01L29/40 ,  H01L29/778

    Abstract: Circuit-Under-Pad (CUP) device topologies for high current lateral GaN power transistors comprise first and second levels of on-chip metallization M1 and M2; M1 defines source, drain and gate finger electrodes of a plurality of sections of a multi-section transistor and a gate bus; M2 defines an overlying contact structure comprising a drain pad and source pads extending over active regions of each section. The drain and source pads of M2 are interconnected by conductive micro-vias to respective underlying drain and source finger electrodes of M1. The pad structure and the micro-via interconnections are configured to reduce current density in self-supported widths of source and drain finger electrodes, i.e. to optimize a maximum current density for each section. For reduced gate loop inductance, part of each source pad is routed over the gate bus. Proposed CUP device structures provide for higher current carrying capability and reduced drain-source resistance.

    Scalable circuit-under-pad device topologies for lateral GaN power transistors
    5.
    发明授权
    Scalable circuit-under-pad device topologies for lateral GaN power transistors 有权

    公开(公告)号：US10529802B2

    公开(公告)日：2020-01-07

    申请号：US15988453

    申请日：2018-05-24

    Applicant: GaN Systems Inc.

    Inventor： Ahmad Mizan ,  Hossein Mousavian ,  Xiaodong Cui

    IPC: H01L29/06 ,  H01L23/482 ,  H01L23/528 ,  H01L23/522 ,  H01L29/205 ,  H01L29/20 ,  H01L29/417 ,  H01L29/40

    Abstract: Circuit-Under-Pad (CUP) device topologies for high current lateral GaN power transistors comprise first and second levels of on-chip metallization M1 and M2; M1 defines source, drain and gate finger electrodes of a plurality of sections of a multi-section transistor and a gate bus; M2 defines an overlying contact structure comprising a drain pad and source pads extending over active regions of each section. The drain and source pads of M2 are interconnected by conductive micro-vias to respective underlying drain and source finger electrodes of M1. The pad structure and the micro-via interconnections are configured to reduce current density in self-supported widths of source and drain finger electrodes, i.e. to optimize a maximum current density for each section. For reduced gate loop inductance, part of each source pad is routed over the gate bus. Proposed CUP device structures provide for higher current carrying capability and reduced drain-source resistance.

    Integrated bidirectional ESD protection circuit for power semiconductor switching devices
    8.
    发明授权
    Integrated bidirectional ESD protection circuit for power semiconductor switching devices 有权

    公开(公告)号：US12107416B2

    公开(公告)日：2024-10-01

    申请号：US17975092

    申请日：2022-10-27

    Applicant: GaN Systems Inc.

    Inventor： Ahmad Mizan ,  Edward Macrobbie

    IPC: H02H9/00 ,  H01L27/02 ,  H02H9/04

    CPC classification number: H02H9/046 ,  H01L27/0255 ,  H01L27/0266 ,  H01L27/0288

    Abstract: A GaN semiconductor power switching device (Qmain) comprising an integrated ESD 1protection circuit is disclosed, which is compatible with driving Qmain with a positive gate-to-source voltage Vgs for turn-on and a negative Vgs for turn-off, during normal operation. The ESD protection circuit is connected between a gate input of Qmain and a source of Qmain, and comprises a clamp transistor Q1, a positive trigger circuit and a negative trigger circuit, for turning on the gate of the clamp transistor Q1 responsive to an ESD event at the gate input of Qmain. The positive and negative trigger circuits each comprise a plurality of diode elements in series, having threshold voltages which are configured so that each of the positive trigger voltage and the negative trigger voltage can be adjusted. The ESD circuit topology requires smaller integrated resistors and can be implemented with reduced layout area compared to conventional integrated ESD circuits.

    Device topology for lateral power transistors with low common source inductance
    9.
    发明授权
    Device topology for lateral power transistors with low common source inductance 有权

    公开(公告)号：US12040257B2

    公开(公告)日：2024-07-16

    申请号：US17974880

    申请日：2022-10-27

    Applicant: GaN Systems Inc.

    Inventor： Ahmad Mizan ,  Edward Macrobbie

    IPC: H01L23/482 ,  H01L29/20 ,  H01L29/778

    CPC classification number: H01L23/4824 ,  H01L29/2003 ,  H01L29/7786

    Abstract: Circuit-Under-Pad (CUP) device topologies for high-current lateral power switching devices are disclosed, in which the interconnect structure and pad placement are configured for reduced source and common source inductance. In an example topology for a power semiconductor device comprising a lateral GaN HEMT, the source bus runs across a center of the active area, substantially centered between first and second extremities of source finger electrodes, with laterally extending tabs contacting the underlying source finger electrodes. The drain bus is spaced from the source bus and comprises laterally extending tabs contacting the underlying drain finger electrodes. The gate bus is centrally placed and runs adjacent the source bus. Preferably, the interconnect structure comprises a dedicated gate return bus to separate the gate drive loop from the power loop. Proposed CUP device structures provide for lower source and common source inductance and/or higher current carrying capability per unit device area.

    Device topology for lateral power transistors with low common source inductance
    10.
    发明授权
    Device topology for lateral power transistors with low common source inductance 有权

    公开(公告)号：US11515235B2

    公开(公告)日：2022-11-29

    申请号：US17117449

    申请日：2020-12-10

    Applicant: GaN Systems Inc.

    Inventor： Ahmad Mizan ,  Edward MacRobbie

    IPC: H01L23/482 ,  H01L29/778 ,  H01L29/20

    Abstract: Circuit-Under-Pad (CUP) device topologies for high-current lateral power switching devices are disclosed, in which the interconnect structure and pad placement are configured for reduced source and common source inductance. In an example topology for a power semiconductor device comprising a lateral GaN HEMT, the source bus runs across a centre of the active area, substantially centered between first and second extremities of source finger electrodes, with laterally extending tabs contacting the underlying source finger electrodes. The drain bus is spaced from the source bus and comprises laterally extending tabs contacting the underlying drain finger electrodes. The gate bus is centrally placed and runs adjacent the source bus. Preferably, the interconnect structure comprises a dedicated gate return bus to separate the gate drive loop from the power loop. Proposed CUP device structures provide for lower source and common source inductance and/or higher current carrying capability per unit device area.

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