公开(公告)号：US11515235B2

公开(公告)日：2022-11-29

申请号：US17117449

申请日：2020-12-10

Applicant: GaN Systems Inc.

Inventor： Ahmad Mizan ,  Edward MacRobbie

IPC: H01L23/482 ,  H01L29/778 ,  H01L29/20

Abstract: Circuit-Under-Pad (CUP) device topologies for high-current lateral power switching devices are disclosed, in which the interconnect structure and pad placement are configured for reduced source and common source inductance. In an example topology for a power semiconductor device comprising a lateral GaN HEMT, the source bus runs across a centre of the active area, substantially centered between first and second extremities of source finger electrodes, with laterally extending tabs contacting the underlying source finger electrodes. The drain bus is spaced from the source bus and comprises laterally extending tabs contacting the underlying drain finger electrodes. The gate bus is centrally placed and runs adjacent the source bus. Preferably, the interconnect structure comprises a dedicated gate return bus to separate the gate drive loop from the power loop. Proposed CUP device structures provide for lower source and common source inductance and/or higher current carrying capability per unit device area.

公开(公告)号：US11527460B2

公开(公告)日：2022-12-13

申请号：US17085137

申请日：2020-10-30

Applicant: GaN Systems Inc.

Inventor： Hossein Mousavian ,  Edward MacRobbie

IPC: H01L23/482 ,  H01L29/778 ,  H01L29/20 ,  H01L29/861 ,  H01L29/417

Abstract: A lateral power semiconductor device structure comprises a pad-over-active topology wherein on-chip interconnect metallization and contact pad placement is optimized to reduce interconnect resistance. For a lateral GaN HEMT, wherein drain, source and gate finger electrodes extend between first and second edges of an active region, the source and drain buses run across the active region at positions intermediate the first and second edges of the active region, interconnecting first and second portions of the source fingers and drain fingers which extend laterally towards the first and second edges of the active region. External contact pads are placed on the source and drain buses. For a given die size, this interconnect structure reduces lengths of current paths in the source and drain metal interconnect, and provides, for example, at least one of lower interconnect resistance, increased current capability per unit active area, and increased active area usage per die.

公开(公告)号：US20240364201A1

公开(公告)日：2024-10-31

申请号：US18309651

申请日：2023-04-28

Applicant: GAN SYSTEMS INC.

Inventor： Yalong LI ,  Yinglai XIA ,  Robert Wayne Mounger ,  Nan XING ,  Edward MacRobbie ,  Zhemin ZHANG

IPC: H02M1/00 ,  H02M1/08 ,  H02M3/156

CPC classification number: H02M1/0009 ,  H02M1/08 ,  H02M3/156

Abstract: A circuit that includes a power transistor and at least one sense transistor and that uses the control drive terminal to not only control the power transistor and the sense transistor, but also to provide power to a current sense circuit. The control nodes of the power transistor and sense transistor are connected, and the input nodes of the power transistor and the sense transistor are also connected. The current sense circuit is connected to the sense transistor control node and is configured to detect current passing through the sense transistor. The current sense circuit is also connected to the control drive terminal and is configured to draw power from the control drive terminal when a high control signal is present on the control drive terminal. Accordingly, the current sense circuit does not require an independent fixed high voltage supply in order to operate.