Invention Grant
- Patent Title: Integration of p-channel and n-channel E-FET III-V devices with optimization of device performance
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Application No.: US16884398Application Date: 2020-05-27
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Publication No.: US11522077B2Publication Date: 2022-12-06
- Inventor: Man-Ho Kwan , Fu-Wei Yao , Chun Lin Tsai , Jiun-Lei Jerry Yu , Ting-Fu Chang
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Eschweiler & Potashnik, LLC
- Main IPC: H01L29/778
- IPC: H01L29/778 ; H01L29/20 ; H01L29/66 ; H01L29/10
Abstract:
Various embodiments of the present disclosure are directed towards an integrated chip a first undoped layer overlies a substrate. A first barrier layer overlies the first undoped layer and has a first thickness. A first doped layer overlies the first barrier layer and is disposed laterally within an n-channel device region of the substrate. A second barrier layer overlies the first barrier layer and is disposed within a p-channel device region that is laterally adjacent to the n-channel device region. The second barrier layer has a second thickness that is greater than the first thickness. A second undoped layer overlies the second barrier layer. A second doped layer overlies the second undoped layer. The second undoped layer and the second doped layer are disposed within the p-channel device region.
Public/Granted literature
- US20210376135A1 INTEGRATION OF P-CHANNEL AND N-CHANNEL E-FET III-V DEVICES WITH OPTIMIZATION OF DEVICE PERFORMANCE Public/Granted day:2021-12-02
Information query
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