A semiconductor memory device according to an embodiment includes a peripheral circuit part supplied with a first voltage, a core circuit part supplied with a second voltage greater than the first voltage, a pre-decoder provided in the peripheral circuit part, input with a signal and outputting a one-hot signal corresponding to the signal, a first wiring provided in the peripheral circuit part, electrically connected to the pre-decoder, and supplied with the one-hot signal, a second wiring provided in the core circuit part, a level shifter provided in the peripheral circuit part, supplied with a first voltage and a second voltage, and transferring the one-hot signal from the first wiring in the peripheral circuit part to the second wiring in the core circuit part, and a memory cell array provided in the core circuit part and operating based on the transferred one-hot signal.