-
公开(公告)号：US11955178B2
公开(公告)日：2024-04-09
申请号：US17695278
申请日：2022-03-15
Applicant: Kioxia Corporation
Inventor： Atsushi Kawasumi
CPC classification number: G11C16/0483 , G11C16/10 , G11C16/26
Abstract: An information processing apparatus has strings connected to a first wiring and connected to second wirings. The string has one end connected to the first wiring and includes transistors being connected to each other, gates of which are connected to the second wirings. The transistors include a first transistor and a second transistor. The first transistor is set to a first threshold according to first data, and the second transistor is set to a second threshold according to second data in a complement relationship with the first data. Two second wirings of the second wirings are connected to gates of the first transistor and the second transistor, and one of the two second wirings is set to a potential level corresponding to third data, and another is set to a potential level corresponding to fourth data in a complement relationship with the third data.
-
公开(公告)号：US11468946B2
公开(公告)日：2022-10-11
申请号：US17345208
申请日：2021-06-11
Applicant: Kioxia Corporation
Inventor： Kazuki Okawa , Hiroyuki Hara , Atsushi Kawasumi
IPC: G11C11/00 , G11C13/00 , H03K19/173 , G11C5/06
Abstract: Provided is a semiconductor storage device including: a substrate having a substrate surface extending in a first direction and a second direction intersecting the first direction; a plurality of first region memory cells provided in a plurality of layers provided parallel to the substrate surface and in a third direction, the first region memory cells being provided above a rectangular shaped first region provided on the substrate surface, the first region having a first side parallel to the first direction and a second side parallel to the second direction when viewed from the third direction intersecting the first direction and the second direction; a plurality of first region wirings provided between the first region memory cells; a plurality of second region memory cells provided in the layers, the second region memory cells being provided above a rectangular shaped second region having a third side parallel to the first direction and a fourth side parallel to the second direction when viewed from the third direction; a plurality of second region wirings provided between the second region memory cells; and a control circuit capable of executing a reading operation.
-
公开(公告)号：US11410721B2
公开(公告)日：2022-08-09
申请号：US17199650
申请日：2021-03-12
Applicant: Kioxia Corporation
Inventor： Atsushi Kawasumi
IPC: G11C11/41 , G11C11/419 , H01L27/11 , G11C11/412
Abstract: A semiconductor memory device of an embodiment includes: a first inverter including a first P-channel and first N-channel transistors; a second inverter including a second P-channel and second N-channel transistors and being cross-connected to the first inverter; a third P-channel transistor; a third N-channel transistor; a first wiring; a second wiring; a third wiring; a fourth wiring; a fifth wiring; a sixth wiring; and a controller that drives the first to sixth wirings. When writing second-level data that is at a higher potential level than first-level data into the drain of the second P-channel transistor and the drain of the second N-channel transistor, the controller puts one of the fifth wiring and the sixth wiring into a floating state.
-
公开(公告)号：US20210090645A1
公开(公告)日：2021-03-25
申请号：US16910826
申请日：2020-06-24
Applicant: Kioxia Corporation
Inventor： Tsuneo Inaba , Atsushi Kawasumi
Abstract: According to an embodiment, a memory device includes a first memory cell and a second memory cell each including a variable resistance element and a switching element, and includes a read and write circuit. The circuit is configured to perform, as a first access, a write operation or a read operation on the first memory cell, and make a second access after the first access. As the second access, data is written into or read from the second memory cell, under a condition based on a type of the first access.
-
公开(公告)号：US12068031B2
公开(公告)日：2024-08-20
申请号：US17901239
申请日：2022-09-01
Applicant: Kioxia Corporation
Inventor： Jun Deguchi , Daisuke Miyashita , Atsushi Kawasumi , Hidehiro Shiga , Shinji Miyano , Shinichi Sasaki
Abstract: A semiconductor storage device includes a memory cell array including a plurality of word line groups and a plurality of blocks corresponding to the plurality of word line groups. Each of word line groups includes a plurality of word lines and each of the blocks includes a plurality of memory cells. The plurality of memory cells of each block are connected to the respective word lines of a corresponding one of the word line groups. The semiconductor storage device includes a row decoder including a plurality of word line group decoders corresponding to the plurality of word line groups, respectively. Each of the plurality of word line group decoders is configured to drive a word line independent from a word line driven in another of the word line groups, when all of the plurality of word line groups are activated in parallel.
-
Patent Agency Ranking
公开(公告)号：US11062770B2
公开(公告)日：2021-07-13
申请号：US16910826
申请日：2020-06-24
Applicant: KIOXIA CORPORATION
Inventor： Tsuneo Inaba , Atsushi Kawasumi
Abstract: According to an embodiment, a memory device includes a first memory cell and a second memory cell each including a variable resistance element and a switching element, and includes a read and write circuit. The circuit is configured to perform, as a first access, a write operation or a read operation on the first memory cell, and make a second access after the first access. As the second access, data is written into or read from the second memory cell, under a condition based on a type of the first access.
-
公开(公告)号：US11004478B2
公开(公告)日：2021-05-11
申请号：US16806053
申请日：2020-03-02
Applicant: Kioxia Corporation
Inventor： Hiroyuki Hara , Atsushi Kawasumi
Abstract: A semiconductor memory device according to an embodiment includes: a substrate having a substrate plane extending in a first direction and a second direction intersecting with the first direction; a first wiring provided above the substrate, the first wiring being provided so that a longitudinal direction extends along the first direction; a second wiring provided above the substrate, the second wiring being separated from the first wiring in the first direction, the second wiring being passed by the same virtual line together with the first wiring, the second wiring being provided so that a longitudinal direction extends along the first direction; a third wiring provided between the first wiring and the second wiring, the third wiring being separated from the first wiring and the second wiring, the third wiring being passed by the same virtual line together with the first wiring and the second wiring, the third wiring being provided so that a longitudinal direction extends along the first direction; a fourth wiring provided above the first wiring, the fourth wiring overlapping with the first wiring when viewed from the above, the fourth wiring being provided so that a longitudinal direction extends along the first direction; a fifth wiring provided over the second wiring and the third wiring, the fifth wiring being separated from the fourth wiring in the first direction, the fifth wiring overlapping with the second wiring and the third wiring when viewed from the above, the fifth wiring being passed by the same virtual line together with the fourth wiring, the fifth wiring being provided so that a longitudinal direction extends along the first direction; a sixth wiring provided over the fourth wiring and the fifth wiring, the sixth wiring overlapping with the fourth wiring and the fifth wiring when viewed from the above, the sixth wiring being provided so that a longitudinal direction extends along the first direction; a plurality of seventh wirings provided between the first wiring and the fourth wiring, between the third wiring and the fifth wiring, and between the second wiring and the fifth wiring, the seventh wirings being provided so that a longitudinal direction extends along the second direction; a plurality of eighth wirings provided between the fourth wiring and the sixth wiring and between the fifth wiring and the sixth wiring, the eighth wirings being provided so that a longitudinal direction extends along the second direction; a plurality of first memory cells provided between the first wiring, the second wiring, and the third wiring and the seventh wirings; a plurality of second memory cells provided between the fourth wiring and the seventh wirings and between the fifth wiring and the seventh wirings, the second memory cells overlapping with the first memory cells when viewed from the above; a plurality of third memory cells provided between the fourth wiring and the eighth wirings and between the fifth wiring and the eighth wirings, the third memory cells overlapping with the second memory cells when viewed from the above; a plurality of fourth memory cells provided between the sixth wiring and the eighth wirings, the fourth memory cells overlapping with the third memory cells when viewed from the above; a first connection wiring provided above the substrate, the first connection wiring being provided at least partially under a portion where the first wiring and the third wiring are separated; a second connection wiring provided between the first wiring and the third wiring so that a longitudinal direction extends along a third direction intersecting with the first direction and the second direction, the second connection wiring connecting the sixth wiring and the first connection wiring; a third connection wiring configured to connect the first wiring and the first connection wiring; a fourth connection wiring configured to connect the third wiring and the first connection wiring; a fifth connection wiring provided above the substrate, the fifth connection wiring being provided at least partially under a portion where the second wiring and the third wiring are separated; and a sixth connection wiring provided between the second wiring and the third wiring so that a longitudinal direction extends along the third direction, the sixth connection wiring connecting the fifth wiring and the fifth connection wiring.
-
公开(公告)号：US12057186B2
公开(公告)日：2024-08-06
申请号：US17471909
申请日：2021-09-10
Applicant: Kioxia Corporation
Inventor： Atsushi Kawasumi
IPC: G11C5/06 , G06F7/544 , G11C11/412 , G11C11/417
CPC classification number: G11C5/063 , G06F7/5443 , G11C11/412 , G11C11/417 , G06F2207/4824
Abstract: A semiconductor integrated circuit has a plurality of memory cells arranged in a first direction and each storing first data, a plurality of first wirings provided to correspond to the plurality of memory cells arranged in the first direction and supplying second data to be multiplied by the first data, and a second wiring pair provided to correspond to the plurality of memory cells arranged in the first direction and that includes one second wiring which is discharged when multiplication data of the first data, stored in each of the plurality of memory cells, and the second data, supplied by the first wiring corresponding to the memory cell, is a first logic; and another second wiring which is discharged when the multiplication data is a second logic.
-
公开(公告)号：US11615834B2
公开(公告)日：2023-03-28
申请号：US17197371
申请日：2021-03-10
Applicant: Kioxia Corporation
Inventor： Atsushi Kawasumi
IPC: G11C11/4094 , G11C11/4097 , G06N3/063 , G06F7/544 , G06N3/08 , G11C5/06
Abstract: A semiconductor storage device has a plurality of memory cells that are arranged in a first direction and store first data, a plurality of first wiring pairs that are provided corresponding to the plurality of memory cells arranged in the first direction, and supply second data multiplied with the first data, a second wiring pair that is provided corresponding to two memory cells adjacent to each other in the first direction, and outputs multiplication data obtained by multiplying the first data stored in the two memory cells with the corresponding second data on the first wiring pair, and a third wiring pair in which potentials are changed depending on an addition result only when the addition result obtained by adding two multiplication data output to the second wiring pair to each other is not zero.
-
公开(公告)号：US11909413B2
公开(公告)日：2024-02-20
申请号：US17471887
申请日：2021-09-10
Applicant: Kioxia Corporation
Inventor： Atsushi Kawasumi
Abstract: A semiconductor integrated circuit has a digital signal generator that generates a binary signal whose logic transitions at a timing according to a discharge amount of a second wiring which is discharged when multiplication data of first data stored in a memory cell and second data on a first wiring is a first logic; and a transition timing detector that detects a timing at which the logic of the binary signal transitions.
-
-
-
-
-
-
-
-
-
Search Results
15
records
(took 0.021 seconds)
