Invention Grant
- Patent Title: FinFET having a gate dielectric comprising a multi-layer structure including an oxide layer with different thicknesses on side and top surfaces of the fins
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Application No.: US16942781Application Date: 2020-07-30
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Publication No.: US11532718B2Publication Date: 2022-12-20
- Inventor: Chen-Hsuan Liao , Chih-Chung Chang , Chun-Heng Chen , Jiun-Ming Kuo
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: JCIPRNET
- Main IPC: H01L29/423
- IPC: H01L29/423 ; H01L29/78 ; H01L29/66 ; H01L21/28 ; H01L21/8234 ; H01L29/51 ; H01L27/088

Abstract:
A semiconductor device includes a substrate, a plurality of insulators, a liner structure and a gate stack. The substrate has fins and trenches in between the fins. The insulators are disposed within the trenches of the substrate. The liner structure is disposed on the plurality of insulators and across the fins, wherein the liner structure comprises sidewall portions and a cap portion, the sidewall portions is covering sidewalls of the fins, the cap portion is covering a top surface of the fins and joined with the sidewall portions, and a maximum thickness T1 of the cap portion is greater than a thickness T2 of the sidewall portions. The gate stack is disposed on the liner structure and across the fins.
Public/Granted literature
- US20220037487A1 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME Public/Granted day:2022-02-03
Information query
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