Invention Grant
- Patent Title: Self-aligned epitaxy layer
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Application No.: US16890803Application Date: 2020-06-02
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Publication No.: US11532735B2Publication Date: 2022-12-20
- Inventor: Kuo-Cheng Chiang , Kuan-Lun Cheng , Chih-Hao Wang
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Sterne, Kessler, Goldstein & Fox P.L.L.C.
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L27/092 ; H01L29/06 ; H01L29/08 ; H01L21/8238 ; H01L21/02 ; H01L29/165 ; H01L29/417 ; H01L29/161 ; H01L29/78

Abstract:
Semiconductor structures including active fin structures, dummy fin structures, epitaxy layers, a Ge containing oxide layer and methods of manufacture thereof are described. By implementing the Ge containing oxide layer on the surface of the epitaxy layers formed on the source/drain regions of some of the FinFET devices, a self-aligned epitaxy process is enabled. By implementing dummy fin structures and a self-aligned etch, both the epitaxy layers and metal gate structures from adjacent FinFET devices are isolated in a self-aligned manner.
Public/Granted literature
- US20200295155A1 SELF-ALIGNED EPITAXY LAYER Public/Granted day:2020-09-17
Information query
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