Invention Grant
- Patent Title: Deadtime optimization for GaN half-bridge and full-bridge switch topologies
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Application No.: US17536542Application Date: 2021-11-29
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Publication No.: US11545889B2Publication Date: 2023-01-03
- Inventor: Yajie Qiu , Larry Spaziani
- Applicant: GaN Systems Inc.
- Applicant Address: CA Ottawa
- Assignee: GaN Systems Inc.
- Current Assignee: GaN Systems Inc.
- Current Assignee Address: CA Ottawa
- Agency: Miltons IP/p.i.
- Main IPC: H02M1/38
- IPC: H02M1/38

Abstract:
Disclosed is a method for deadtime optimization in a half-bridge switch or full-bridge switch wherein high-side and low-side switches comprise GaN transistors; a circuit for implementing the method; and a power switching system comprising a GaN half-bridge or a GaN full-bridge and a deadtime optimization system. The circuit comprises a drain current bump filter for generating a current charge output; and circuit elements for comparing the current charge output to a reference current charge Coss and generating a deadtime adjust signal. The deadtime adjust signal may be used to adjust deadtime to reduce or minimize deadtime, and deadtime losses, while avoiding cross-conduction.
Public/Granted literature
- US20220209650A1 DEADTIME OPTIMIZATION FOR GaN HALF-BRIDGE AND FULL-BRIDGE SWITCH TOPOLOGIES Public/Granted day:2022-06-30
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