Deadtime optimization for GaN half-bridge and full-bridge switch topologies

    公开(公告)号:US11545889B2

    公开(公告)日:2023-01-03

    申请号:US17536542

    申请日:2021-11-29

    申请人: GaN Systems Inc.

    IPC分类号: H02M1/38

    摘要: Disclosed is a method for deadtime optimization in a half-bridge switch or full-bridge switch wherein high-side and low-side switches comprise GaN transistors; a circuit for implementing the method; and a power switching system comprising a GaN half-bridge or a GaN full-bridge and a deadtime optimization system. The circuit comprises a drain current bump filter for generating a current charge output; and circuit elements for comparing the current charge output to a reference current charge Coss and generating a deadtime adjust signal. The deadtime adjust signal may be used to adjust deadtime to reduce or minimize deadtime, and deadtime losses, while avoiding cross-conduction.

    Power modules for ultra-fast wide-bandgap power switching devices

    公开(公告)号:US11735492B2

    公开(公告)日:2023-08-22

    申请号:US17465345

    申请日:2021-09-02

    申请人: GaN Systems Inc.

    摘要: Low inductance power modules for ultra-fast wide-bandgap semiconductor power switching devices are disclosed. Conductive tracks define power buses for a switching topology, e.g. comprising GaN E-HEMTs, with power terminals extending from the power buses through the housing to provide a heatsink-to-busbar distance which meets creepage and clearance requirements. Low-profile, low-inductance terminals for gate and source-sense connections extend from contact areas located adjacent each power switching device to provide for a low inductance gate drive loop, for high di/dt switching. The gate driver board is mounted on the low-profile terminals, inside or outside of the housing, with decoupling capacitors provided on the driver board. For paralleled switches, additional terminals, which are referred to as dynamic performance pins, are provided to the power buses. These pins are configured to provide a low inductance path for high-frequency current and balance inductances of the power commutation loops for each switch.

    Active gate voltage control circuit for burst mode and protection mode operation of power switching transistors

    公开(公告)号:US11736100B2

    公开(公告)日:2023-08-22

    申请号:US17308423

    申请日:2021-05-05

    申请人: GaN Systems Inc.

    IPC分类号: H03K17/0812 H03K17/16

    CPC分类号: H03K17/08122 H03K17/163

    摘要: An active gate voltage control circuit for a gate driver of a power semiconductor switching device comprising a power semiconductor transistor, such as a GaN HEMT, provides active gate voltage control comprising current burst mode operation and protection mode operation. The gate-source turn-on voltage Vgs(on) is increased in burst mode operation, to allow for a temporary increase of saturation current. In protection mode operation, a multi-stage turn-off may be implemented, comprising reducing Vgs(on) to implement fast soft turn-off, followed by full turn-off to bring Vgs(on) below threshold voltage, to reduce switching transients such as Vds spikes. Circuits of example embodiments provide for burst mode operation for enhanced saturation current, to increase robustness of enhancement mode GaN power switching devices, e.g. under overcurrent and short circuit conditions, or to provide active gate voltage control which adjusts dynamically to specific operating conditions or events.

    Power modules for ultra-fast wide-bandgap power switching devices

    公开(公告)号:US11183440B2

    公开(公告)日:2021-11-23

    申请号:US16705696

    申请日:2019-12-06

    申请人: GaN Systems Inc.

    摘要: Low inductance power modules for ultra-fast wide-bandgap semiconductor power switching devices are disclosed. Conductive tracks define power buses for a switching topology, e.g. comprising GaN E-HEMTs, with power terminals extending from the power buses through the housing to provide a heatsink-to-busbar distance which meets creepage and clearance requirements. Low-profile, low-inductance terminals for gate and source-sense connections extend from contact areas located adjacent each power switching device to provide for a low inductance gate drive loop, for high di/dt switching. The gate driver board is mounted on the low-profile terminals, inside or outside of the housing, with decoupling capacitors provided on the driver board. For paralleled switches, additional terminals, which are referred to as dynamic performance pins, are provided to the power buses. These pins are configured to provide a low inductance path for high-frequency current and balance inductances of the power commutation loops for each switch.

    Hybrid power stage and gate driver circuit

    公开(公告)号:US11677396B2

    公开(公告)日:2023-06-13

    申请号:US17123316

    申请日:2020-12-16

    申请人: GaN Systems Inc.

    IPC分类号: H03K17/687 H03K17/567

    摘要: Hybrid power switching stages and driver circuits are disclosed. An example semiconductor power switching device comprises a high-side switch and a low-side switch connected in a half-bridge configuration, wherein the high-side switch comprises a GaN power transistor and the low-side switch comprises a Si MOSFET. The Si—GaN hybrid switching stage provides enhanced performance, e.g. reduced switching losses, in a cost-effective solution which takes advantage of characteristics of power switching devices comprising both GaN power transistors and Si MOSFETs. Also disclosed is a gate driver for the Si—GaN hybrid switching stage, and a semiconductor power switching stage comprising the gate driver and a Si—GaN hybrid power switching device having a half-bridge or full-bridge switching topology.

    GaN transistor with integrated drain voltage sense for fast overcurrent and short circuit protection

    公开(公告)号:US11082039B2

    公开(公告)日:2021-08-03

    申请号:US15807021

    申请日:2017-11-08

    申请人: GaN Systems Inc.

    摘要: A GaN power switching device comprises a GaN transistor switch SW_MAIN has an integrated drain voltage sense circuit, which comprises GaN sense transistor SW_SEN and GaN sense resistor RSEN, which at turn-on form a resistive divider for sensing the drain voltage of SW_MAIN to provide a drain voltage sense output VDSEN. Fault detection logic circuitry of a driver circuit generates a fault signal FLT when VDSEN reaches or exceeds a reference voltage Vref, which triggers fast turn-off of the gate of SW_MAIN, e.g. within less than 100 ns of an overcurrent or short circuit condition. During turn-off, RSEN resets VDSEN to zero. For two stage turn-off, the driver circuit further comprises fast soft turn-off circuitry which is triggered first by the fault signal to pull-down the gate voltage to the threshold voltage, followed by a delay before full turn-off of the gate of SW_MAIN by the gate driver.

    Enhanced performance hybrid three-level inverter/rectifier

    公开(公告)号:US10778114B2

    公开(公告)日:2020-09-15

    申请号:US16251696

    申请日:2019-01-18

    申请人: GaN Systems Inc.

    摘要: A 3-level T-type neutral point clamped (NPC) inverter/rectifier is disclosed in which neutral point clamping is dynamically enabled/disabled responsive to load, e.g. enabled at low load for operation in a first mode as a 3-level inverter/rectifier and disabled at high/peak load for operation in a second mode as a 2-level inverter/rectifier. When the neutral clamping leg is enabled only under low load and low current, middle switches S2 and S3 can be smaller, lower cost devices with a lower current rating. Si, SiC, GaN and hybrid implementations provide options to optimize efficiency for specific load ratios and applications. For reduced switching losses and enhanced performance of inverters based on Si-IGBT power switches, a hybrid implementation of the dual-mode T-type NPC inverter is proposed, wherein switches S1 and S4 comprise Si-IGBTs and switches S2 and S3 of the neutral clamping leg comprise GaN HEMTs. Applications include electric vehicle traction inverters.