Invention Grant
- Patent Title: Serial data interface with reduced loop delay
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Application No.: US17143679Application Date: 2021-01-07
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Publication No.: US11550749B2Publication Date: 2023-01-10
- Inventor: Manoj Kumar , Kailash Kumar , Nicolas Demange
- Applicant: STMicroelectronics International N.V. , STMicroelectronics (Rousset) SAS
- Applicant Address: CH Geneva; FR Rousset
- Assignee: STMicroelectronics International N.V.,STMicroelectronics (Rousset) SAS
- Current Assignee: STMicroelectronics International N.V.,STMicroelectronics (Rousset) SAS
- Current Assignee Address: CH Geneva; FR Rousset
- Agency: Crowe & Dunlevy
- Main IPC: G06F13/42
- IPC: G06F13/42 ; G06F1/06

Abstract:
A serial peripheral interface (SPI) device includes a serial clock (SCK) pad receiving a serial clock, first and second Schmitt triggers directly electrically connected to the SCK pad to selectively respectively generate first and second clocks in response to rising and falling edges of the serial clock, first and second flip flops clocked by the first and second clocks to output bits of data to a data node, a multiplexer having an input coupled to the data node and an output coupled to driving circuitry, and driving circuitry transmitting data via a master-in-slave-out (MISO) pad.
Public/Granted literature
- US20210248104A1 SERIAL DATA INTERFACE WITH REDUCED LOOP DELAY Public/Granted day:2021-08-12
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