Invention Grant
- Patent Title: Memory system
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Application No.: US17464552Application Date: 2021-09-01
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Publication No.: US11561854B2Publication Date: 2023-01-24
- Inventor: Noboru Okamoto , Toshikatsu Hida
- Applicant: KIOXIA CORPORATION
- Applicant Address: JP Tokyo
- Assignee: KIOXIA CORPORATION
- Current Assignee: KIOXIA CORPORATION
- Current Assignee Address: JP Tokyo
- Agency: Kim & Stewart LLP
- Priority: JPJP2021-014718 20210202
- Main IPC: G06F11/10
- IPC: G06F11/10 ; G11C16/26 ; G11C16/20 ; G11C16/04

Abstract:
A memory system connectable to a host, includes a non-volatile memory including a plurality of memory cell transistors and a controller configured to execute read operations on the non-volatile memory. The controller executes one or more first read operations on the non-volatile memory to obtain read data using read voltages that are determined from one of a plurality of entries stored in a shift table, and performs error correction on the read data, until the error correction is successful, and when the error correction on the read data is successful, records an index corresponding to the entry stored in the shift table that was used in obtaining the successfully error-corrected read data. The controller executes a second read operation on the non-volatile memory to obtain read data using read voltages that are determined from the entry stored in the shift table corresponding to the recorded index.
Public/Granted literature
- US20220245028A1 MEMORY SYSTEM Public/Granted day:2022-08-04
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