公开(公告)号：US20230122474A1

公开(公告)日：2023-04-20

申请号：US18086206

申请日：2022-12-21

Applicant: KIOXIA CORPORATION

Inventor： Noboru Okamoto ,  Toshikatsu Hida

IPC: G06F11/10 ,  G11C16/26 ,  G11C16/20 ,  G11C16/04

Abstract: A memory system connectable to a host, includes a non-volatile memory including a plurality of memory cell transistors and a controller configured to execute read operations on the non-volatile memory. The controller executes one or more first read operations on the non-volatile memory to obtain read data using read voltages that are determined from one of a plurality of entries stored in a shift table, and performs error correction on the read data, until the error correction is successful, and when the error correction on the read data is successful, records an index corresponding to the entry stored in the shift table that was used in obtaining the successfully error-corrected read data. The controller executes a second read operation on the non-volatile memory to obtain read data using read voltages that are determined from the entry stored in the shift table corresponding to the recorded index.

公开(公告)号：US11874738B2

公开(公告)日：2024-01-16

申请号：US18086206

申请日：2022-12-21

Applicant: KIOXIA CORPORATION

Inventor： Noboru Okamoto ,  Toshikatsu Hida

IPC: G06F11/10 ,  G11C16/26 ,  G11C16/20 ,  G11C16/04

CPC classification number: G06F11/1068 ,  G11C16/0483 ,  G11C16/20 ,  G11C16/26

Abstract: A memory system connectable to a host, includes a non-volatile memory including a plurality of memory cell transistors and a controller configured to execute read operations on the non-volatile memory. The controller executes one or more first read operations on the non-volatile memory to obtain read data using read voltages that are determined from one of a plurality of entries stored in a shift table, and performs error correction on the read data, until the error correction is successful, and when the error correction on the read data is successful, records an index corresponding to the entry stored in the shift table that was used in obtaining the successfully error-corrected read data. The controller executes a second read operation on the non-volatile memory to obtain read data using read voltages that are determined from the entry stored in the shift table corresponding to the recorded index.

公开(公告)号：US11561854B2

公开(公告)日：2023-01-24

申请号：US17464552

申请日：2021-09-01

Applicant: KIOXIA CORPORATION

Inventor： Noboru Okamoto ,  Toshikatsu Hida

IPC: G06F11/10 ,  G11C16/26 ,  G11C16/20 ,  G11C16/04

Abstract: A memory system connectable to a host, includes a non-volatile memory including a plurality of memory cell transistors and a controller configured to execute read operations on the non-volatile memory. The controller executes one or more first read operations on the non-volatile memory to obtain read data using read voltages that are determined from one of a plurality of entries stored in a shift table, and performs error correction on the read data, until the error correction is successful, and when the error correction on the read data is successful, records an index corresponding to the entry stored in the shift table that was used in obtaining the successfully error-corrected read data. The controller executes a second read operation on the non-volatile memory to obtain read data using read voltages that are determined from the entry stored in the shift table corresponding to the recorded index.