Invention Grant
- Patent Title: Cache operations in a hybrid dual in-line memory module
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Application No.: US17450124Application Date: 2021-10-06
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Publication No.: US11561902B2Publication Date: 2023-01-24
- Inventor: Paul Stonelake , Horia C. Simionescu , Samir Mittal , Robert W. Walker , Anirban Ray , Gurpreet Anand
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Lowenstein Sandler LLP
- Main IPC: G06F12/0811
- IPC: G06F12/0811 ; G06F12/0897 ; G06F12/0888 ; G06F12/0862

Abstract:
A system includes a first memory device of a first memory type, a second memory device of a second memory type, and a third memory device of a third memory type. The system further includes a processing device to retrieve one or more sections of data from the first memory device comprising a first memory type, and retrieve one or more remaining sections of data from the second memory device comprising a second memory type, wherein the one or more remaining sections of data from the second memory device are associated with the one or more sections of data from the first memory device. The processing device is further to combine the one or more sections of data from the first memory device comprising the first memory type with the one or more remaining sections of each of data from the second memory device comprising the second memory type into a contiguous page, and copy the contiguous page to a third memory device comprising a third memory type.
Public/Granted literature
- US20220027271A1 CACHE OPERATIONS IN A HYBRID DUAL IN-LINE MEMORY MODULE Public/Granted day:2022-01-27
Information query
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