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公开(公告)号：US20220027271A1
公开(公告)日：2022-01-27
申请号：US17450124
申请日：2021-10-06
Applicant: Micron Technology, Inc.
Inventor： Paul Stonelake , Horia C. Simionescu , Samir Mittal , Robert W. Walker , Anirban Ray , Gurpreet Anand
IPC: G06F12/0811 , G06F12/0897 , G06F12/0888 , G06F12/0862
Abstract: A system includes a first memory device of a first memory type, a second memory device of a second memory type, and a third memory device of a third memory type. The system further includes a processing device to retrieve one or more sections of data from the first memory device comprising a first memory type, and retrieve one or more remaining sections of data from the second memory device comprising a second memory type, wherein the one or more remaining sections of data from the second memory device are associated with the one or more sections of data from the first memory device. The processing device is further to combine the one or more sections of data from the first memory device comprising the first memory type with the one or more remaining sections of each of data from the second memory device comprising the second memory type into a contiguous page, and copy the contiguous page to a third memory device comprising a third memory type.
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公开(公告)号：US20210200703A1
公开(公告)日：2021-07-01
申请号：US16948005
申请日：2020-08-27
Applicant: Micron Technology, Inc.
Inventor： Horia C. Simionescu , Xiaodong Wang , Venkata Yaswanth Raparti
Abstract: A processing device in a memory sub-system iteratively processes input/output (I/O) operations corresponding to a plurality of logical devices associated with a memory device. Tor each of the plurality of logical devices, the processing includes identifying a current logical device, determining one or more I/O operations in queue for the current logical device, and determining a number of operation credits associated with the current logical device. The number of credits is based at least in part on a set of quality of service (QoS) parameters for the current logical device. The processing further includes responsive to determining that the number of operation credits satisfies a threshold condition, performing the one or more I/O operations for the current logical device and identifying a subsequent logical device of the plurality of logical devices.
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公开(公告)号：US20240160553A1
公开(公告)日：2024-05-16
申请号：US18388610
申请日：2023-11-10
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Raja V.S. Halaharivi , Prateek Sharma , Horia C. Simionescu
IPC: G06F11/34
CPC classification number: G06F11/3428
Abstract: A memory system includes a memory device and a processing device coupled to the memory device, the processing device is to present a plurality of physical or virtual functions (PFs/VFs) to a host computing system; set, for each of the plurality of PFs/VFs, a value of a credit counter to an initial value associated with a Quality of Service (QoS) parameter of a respective PF/VF; responsive to fetching an original command received from the host computing system associated with a specified PF/VF, decrement the value of the credit counter associated with the specified PF/VF; responsive to receiving a reintroduced command associated with the specified PF/VF after the original command, increment the value of the credit counter; determine whether the value of the credit counter is not higher than a threshold value; and responsive to determining that the value of the credit counter is higher than the threshold value, continue fetching a subsequent command associated with the specified PF/VF.
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公开(公告)号：US20230350754A1
公开(公告)日：2023-11-02
申请号：US17733519
申请日：2022-04-29
Applicant: Micron Technology, Inc.
Inventor： Horia C. Simionescu , Ramkumar Venkatachalam , Anirban Kundu
CPC classification number: G06F11/1415 , G11C29/08 , G06F2201/82
Abstract: A method includes receiving signaling indicative of performance of a reset operation involving a first physical function associated with a controller of a memory device and initiating a first timer that corresponds to an amount of time available for the first physical function associated with the controller of the memory device to complete execution of pending commands. The method further includes initiating a second timer that corresponds to an amount of time available for a second physical function associated with the controller of the memory device to complete execution of pending commands and initiating a third timer that corresponds to an amount of time available for the second physical function associated with the controller of the memory device to join a recovery operation that is instigated as a result of performance of the reset operation.
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公开(公告)号：US20230176731A1
公开(公告)日：2023-06-08
申请号：US17543039
申请日：2021-12-06
Applicant: Micron Technology, Inc.
Inventor： Horia C. Simionescu , Chung Kuang Chin
IPC: G06F3/06 , G06F12/10 , G06F12/123
CPC classification number: G06F3/0604 , G06F12/10 , G06F12/124 , G06F3/0644 , G06F3/0673 , G06F12/0802
Abstract: Managed units (MUs) of data can be stored on a memory device according to a slice-based layout. A slice of the slice-based layout can include a plurality of stripes, each of the stripes including respective partitions and respective MUs of data. A subset of the stripes each include a quantity of partitions and a first quantity of MUs of data. Another subset of the stripes each include a lesser quantity of partitions and a lesser quantity of MUs of data.
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Patent Agency Ranking
公开(公告)号：US11442656B2
公开(公告)日：2022-09-13
申请号：US17182077
申请日：2021-02-22
Applicant: Micron Technology, Inc.
Inventor： Horia C. Simionescu , Rohitkumar Makhija , Peng-Cheng Chen , Jung Sheng Hoei
IPC: G06F3/06
Abstract: An indication that one or more program operations have been interrupted as a result of a read operation can be received at a first controller component associated with a memory sub-system. Context data associated with interrupted program operations can be received at the first controller component. A control sequence based on the context data can be generated at the first controller component. The control sequence can indicate how a second controller component associated with the memory sub-system interacts with a memory component of the memory sub-system to perform the read operation and to resume the interrupted program operations. The control sequence can further specify one or more additional operations that are associated with copying data of the interrupted program operations between first and second memory locations of the memory component. The control sequence can be provided to the second controller component.
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公开(公告)号：US11169920B2
公开(公告)日：2021-11-09
申请号：US16573305
申请日：2019-09-17
Applicant: Micron Technology, Inc.
Inventor： Paul Stonelake , Horia C. Simionescu , Samir Mittal , Robert M. Walker , Anirban Ray , Gurpreet Anand
IPC: G06F12/0811 , G06F12/0897 , G06F12/0888 , G06F12/0862
Abstract: A system includes a first memory component of a first memory type, a second memory component of a second memory type with a higher access latency than the first memory component, and a third memory component of a third memory type with a higher access latency than the first and second memory components. The system further includes a processing device to identify a section of a data page stored in the first memory component, and access patterns associated with the data page and the section of the data page. The processing device determines to cache the data page at the second memory component based on the access patterns, copying the section of the data page stored in the first memory component to the second memory component. The processing device then copies additional sections of the data page stored at the third memory component to the second memory component.
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公开(公告)号：US20230176978A1
公开(公告)日：2023-06-08
申请号：US17541786
申请日：2021-12-03
Applicant: Micron Technology, Inc.
Inventor： Chung Kuang Chin , Di Hsien Ngu , Horia C. Simionescu
IPC: G06F12/1009
CPC classification number: G06F12/1009 , G06F2212/651
Abstract: Translated addresses of a memory device can be stored in a first LUT maintained by control circuitry. Untranslated addresses can be stored in a second LUT maintained by the control circuitry. In response to a translation request for a particular translated address of the memory device corresponding to a target untranslated address, an index of the second LUT associated with the target untranslated address can be determined, the index of the second LUT can be mapped to an index of the first LUT, and the particular translated address corresponding to the target untranslated address can be retrieved from the first LUT.
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公开(公告)号：US11561902B2
公开(公告)日：2023-01-24
申请号：US17450124
申请日：2021-10-06
Applicant: Micron Technology, Inc.
Inventor： Paul Stonelake , Horia C. Simionescu , Samir Mittal , Robert W. Walker , Anirban Ray , Gurpreet Anand
IPC: G06F12/0811 , G06F12/0897 , G06F12/0888 , G06F12/0862
Abstract: A system includes a first memory device of a first memory type, a second memory device of a second memory type, and a third memory device of a third memory type. The system further includes a processing device to retrieve one or more sections of data from the first memory device comprising a first memory type, and retrieve one or more remaining sections of data from the second memory device comprising a second memory type, wherein the one or more remaining sections of data from the second memory device are associated with the one or more sections of data from the first memory device. The processing device is further to combine the one or more sections of data from the first memory device comprising the first memory type with the one or more remaining sections of each of data from the second memory device comprising the second memory type into a contiguous page, and copy the contiguous page to a third memory device comprising a third memory type.
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公开(公告)号：US11494306B2
公开(公告)日：2022-11-08
申请号：US17003336
申请日：2020-08-26
Applicant: Micron Technology, Inc.
IPC: G06F12/084 , G06F3/06 , G06F13/16 , G11C14/00
Abstract: Systems and methods are disclosed including a first memory component, a second memory component having a lower access latency than the first memory component and acting as a cache for the first memory component, and a processing device operatively coupled to the first and second memory components. The processing device can perform operations including receiving a data access operation and, responsive to determining that a data structure includes an indication of an outstanding data transfer of data associated with a physical address of the data access operation, determining whether an operation to copy the data, associated with the physical address, from the first memory component to the second memory component is scheduled to be executed. The processing device can further perform operations including determining to delay a scheduling of an execution of the data access operation until the operation to copy the data is executed.
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