公开(公告)号：US20250060879A1

公开(公告)日：2025-02-20

申请号：US18935320

申请日：2024-11-01

Applicant: Micron Technology, Inc.

Inventor： Samir Mittal ,  Gurpreet Anand ,  Ying Yu Tai ,  Cheng Yuan Wu

IPC: G06F3/06 ,  G06F9/445 ,  G06F13/16 ,  G06F13/42 ,  G11C16/20

Abstract: A computing system having a memory component with an embedded media controller. The memory component is encapsulated within an integrated circuit (IC) package. The embedded controller within the IC package is configured to: receive incoming packets, via a serial communication interface of the controller, from a serial connection outside of the IC package; convert the incoming packets into commands and addresses according to a predetermined serial communication protocol; operate memory units encapsulated within the IC package according to the commands and the addresses; convert results of at least a portion of the commands into outgoing packets; and transmit the outgoing packets via the serial communication interface to the serial connection outside of the IC package.

公开(公告)号：US20240272835A1

公开(公告)日：2024-08-15

申请号：US18645761

申请日：2024-04-25

Applicant: Micron Technology, Inc.

Inventor： Parag R. Maharana ,  Anirban Ray ,  Gurpreet Anand ,  Samir Mittal

IPC: G06F3/06 ,  G06F12/00 ,  G06F13/28 ,  G06F15/173 ,  G11C14/00 ,  H04L67/1097

CPC classification number: G06F3/067 ,  G06F12/00 ,  G06F13/28 ,  G06F15/17331 ,  G11C14/0009 ,  H04L67/1097

Abstract: A memory system having memory components, a remote direct memory access (RDMA) network interface card (RNIC), and a host system, and configured to: allocate a page of virtual memory for an application; map the page of virtual memory to a page of physical memory in the memory components; instruct the RNIC to perform an RDMA operation; perform, during the RDMA operation, a data transfer between the page of physical memory in the plurality of memory components and a remote device that is connected via a computer network to the remote direct memory access network interface card; and at least for a duration of the data transfer, lock a mapping between the page of virtual memory and the page of physical memory in the memory components.

公开(公告)号：US11874779B2

公开(公告)日：2024-01-16

申请号：US17112748

申请日：2020-12-04

Applicant: Micron Technology, Inc.

Inventor： Wei Wang ,  Jiangli Zhu ,  Ying Yu Tai ,  Samir Mittal

IPC: G06F13/16 ,  G06F3/06 ,  G11C7/10

CPC classification number: G06F13/1642 ,  G06F3/061 ,  G06F3/0659 ,  G06F3/0671 ,  G11C7/1045 ,  G06F2213/16

Abstract: A data bus is determined to be in a write mode. Whether a number of memory queues that identify at least one write operation satisfies a threshold criterion is determined. The memory queues include identifiers of one or more write operations and identifiers of one or more read operations. Responsive to determining that the number of memory queues satisfies the threshold criterion, a write operation from the memory queues is transmitted over the data bus.

公开(公告)号：US20220283949A1

公开(公告)日：2022-09-08

申请号：US17824685

申请日：2022-05-25

Applicant: Micron Technology, Inc.

Inventor： Anirban Ray ,  Paul Stonelake ,  Samir Mittal ,  Gurpreet Anand

IPC: G06F12/0868 ,  G06F13/28 ,  G06F3/06 ,  G06F13/16 ,  G06F13/42

Abstract: A processing device in a host system monitors a data temperature of a plurality of memory pages stored in a host-addressable region of a cache memory component operatively coupled with the host system. The processing device determines that a first memory page of the plurality of memory pages satisfies a first threshold criterion pertaining to the data temperature of the first memory page and sends a first migration command indicating the first memory page to a direct memory access (DMA) engine executing on a memory-mapped storage component operatively coupled with the cache memory component and with the memory-mapped storage component via a peripheral component interconnect express (PCIe) bus. The first migration command causes the DMA engine to initiate a first DMA transfer of the first memory page from the cache memory component to a host-addressable region of the memory-mapped storage component.

公开(公告)号：US11379373B2

公开(公告)日：2022-07-05

申请号：US16539139

申请日：2019-08-13

Applicant: Micron Technology, Inc.

Inventor： Anirban Ray ,  Paul Stonelake ,  Samir Mittal ,  Gurpreet Anand

IPC: G06F12/0868 ,  G06F13/28 ,  G06F3/06 ,  G06F13/16 ,  G06F13/42

Abstract: A processing device in a host system monitors a data temperature of a plurality of memory pages stored in a host-addressable region of a cache memory component operatively coupled with the host system. The processing device determines that a first memory page of the plurality of memory pages satisfies a first threshold criterion pertaining to the data temperature of the first memory page and sends a first migration command indicating the first memory page to a direct memory access (DMA) engine executing on a memory-mapped storage component operatively coupled with the cache memory component and with the memory-mapped storage component via a peripheral component interconnect express (PCIe) bus. The first migration command causes the DMA engine to initiate a first DMA transfer of the first memory page from the cache memory component to a host-addressable region of the memory-mapped storage component.

公开(公告)号：US11169920B2

公开(公告)日：2021-11-09

申请号：US16573305

申请日：2019-09-17

Applicant: Micron Technology, Inc.

Inventor： Paul Stonelake ,  Horia C. Simionescu ,  Samir Mittal ,  Robert M. Walker ,  Anirban Ray ,  Gurpreet Anand

IPC: G06F12/0811 ,  G06F12/0897 ,  G06F12/0888 ,  G06F12/0862

Abstract: A system includes a first memory component of a first memory type, a second memory component of a second memory type with a higher access latency than the first memory component, and a third memory component of a third memory type with a higher access latency than the first and second memory components. The system further includes a processing device to identify a section of a data page stored in the first memory component, and access patterns associated with the data page and the section of the data page. The processing device determines to cache the data page at the second memory component based on the access patterns, copying the section of the data page stored in the first memory component to the second memory component. The processing device then copies additional sections of the data page stored at the third memory component to the second memory component.

公开(公告)号：US11016890B2

公开(公告)日：2021-05-25

申请号：US16167189

申请日：2018-10-22

Applicant: Micron Technology, Inc.

Inventor： Paul Stonelake ,  Samir Mittal

IPC: G06F12/0806 ,  G06F3/06

Abstract: A computing system having a power loss detector and memory components to store data associated with write commands received from a host system. The write commands are flushed from a protected write queue of the host system responsive to detecting an impending loss of power. The computing system further includes a processing device to receive the write commands over a memory interface. The processing device is further to, responsive to detecting the loss of power by the detector: disable the memory interface, and store the data associated with write commands that are received prior to disabling the memory interface. The data is stored in one or more of the memory components using power supplied by one or more capacitors.

公开(公告)号：US20210027812A1

公开(公告)日：2021-01-28

申请号：US16949036

申请日：2020-10-09

Applicant: Micron Technology, Inc.

Inventor： Edward McGlaughlin ,  Ying Yu Tai ,  Samir Mittal

IPC: G11C5/14 ,  G11C13/00 ,  G11C11/4074 ,  G06F3/06

Abstract: A processing device determines a subset of a plurality of blocks from a volatile memory device of a memory sub-system, retrieves the subset of the plurality of blocks from the volatile memory device, and writes the subset of the plurality of blocks to a non-volatile cross point array memory device of the memory sub-system using a first type of write operation. The processing device further receives an indication of a power loss in the memory sub-system, and responsive to receiving the indication of the power loss, writes a remainder of the plurality of blocks to the non-volatile cross point array memory device using a second type of write operation.

公开(公告)号：US10671460B2

公开(公告)日：2020-06-02

申请号：US16054890

申请日：2018-08-03

Applicant: Micron Technology, Inc.

Inventor： Samir Mittal ,  Gurpreet Anand ,  Anirban Ray ,  Parag R. Maharana

IPC: G06F3/00 ,  G06F9/54 ,  G06F15/173 ,  G06N3/08 ,  G06F12/0864 ,  G06F13/42

Abstract: A memory system having a plurality of memory components and a controller, operatively coupled to the plurality of memory components to: store data in the memory components; communicate with a host system via a bus; service the data to the host system via communications over the bus; communicate with a processing device that is separate from the host system using a message passing interface over the bus; and provide data access to the processing device through communications made using the message passing interface over the bus.

公开(公告)号：US20200082901A1

公开(公告)日：2020-03-12

申请号：US16123911

申请日：2018-09-06

Applicant: Micron Technology, Inc.

Inventor： Samir Mittal ,  Ying Yu Tai ,  Cheng Yuan Wu ,  Jiangli Zhu

IPC: G11C29/48 ,  G11C29/56 ,  G11C29/52 ,  G11C29/14 ,  G11C29/44 ,  G06F11/10

Abstract: A processing device of a sequencer component can receive data from a controller that is external to the sequencer component. The processing device of the sequencer component can perform an error correction operation on the data received from the controller that is external to the sequencer component to generate a code word associated with the data. The code word can be stored at a memory component coupled with the sequencer component.