Invention Grant
- Patent Title: Sequential wordline erase verify schemes
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Application No.: US17335132Application Date: 2021-06-01
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Publication No.: US11574690B2Publication Date: 2023-02-07
- Inventor: Ronit Roneel Prakash , Jiun-Horng Lai , Chengkuan Yin , Shinji Sato
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Lowenstein Sandler LLP
- Main IPC: G11C16/34
- IPC: G11C16/34 ; G11C16/04

Abstract:
A system includes a memory device including a memory array including a plurality of wordline groups and control logic, operatively coupled with the memory array, to perform operation including causing a first erase verify to be performed sequentially with respect to each wordline group of the plurality of wordline groups, identifying a set of failing wordline groups determined to have failed the first erase verify, and causing a second erase verify to be performed sequentially with respect to each wordline group of the set of failing wordline groups.
Public/Granted literature
- US20220383963A1 SEQUENTIAL WORDLINE ERASE VERIFY SCHEMES Public/Granted day:2022-12-01
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