公开(公告)号：US20240361945A1

公开(公告)日：2024-10-31

申请号：US18645713

申请日：2024-04-25

Applicant: Micron Technology, Inc.

Inventor： Zhongguang Xu ,  Ronit Roneel Prakash

IPC: G06F3/06

CPC classification number: G06F3/0652 ,  G06F3/0604 ,  G06F3/0679

Abstract: Aspects of the present disclosure configure a system component, such as a memory sub-system controller, to efficiently erase memory blocks. The controller receives a request to erase an individual memory component of a set of memory components. The controller applies an erase pulse to the individual memory component in response to the request. The controller, following application of the erase pulse, applies a pre-program pulse to the individual memory component.

公开(公告)号：US12002524B2

公开(公告)日：2024-06-04

申请号：US18085783

申请日：2022-12-21

Applicant: Micron Technology, Inc.

Inventor： Ronit Roneel Prakash ,  Jiun-Horng Lai ,  Chengkuan Yin ,  Shinji Sato

IPC: G11C16/34 ,  G11C16/04

CPC classification number: G11C16/3445 ,  G11C16/0483

Abstract: A memory device includes a memory array including a plurality of wordline groups, each wordline group of the plurality of wordline groups including a set of even wordlines and a set of odd wordlines, and control logic, operatively coupled with the memory array, to perform operations including identifying a set of failing wordline groups from the plurality of wordline groups, the set of failing wordline groups including at least one failing wordline group determined to have failed a first erase verify of an erase verify process, and causing a second erase verify of the erase verify process to be performed sequentially with respect to each failing wordline group of the set of failing wordline groups.

公开(公告)号：US20230117364A1

公开(公告)日：2023-04-20

申请号：US18085783

申请日：2022-12-21

Applicant: Micron Technology, Inc.

Inventor： Ronit Roneel Prakash ,  Jiun-Horng Lai ,  Chengkuan Yin ,  Shinji Sato

IPC: G11C16/34 ,  G11C16/04

Abstract: A memory device includes a memory array including a plurality of wordline groups, each wordline group of the plurality of wordline groups including a set of even wordlines and a set of odd wordlines, and control logic, operatively coupled with the memory array, to perform operations including identifying a set of failing wordline groups from the plurality of wordline groups, the set of failing wordline groups including at least one failing wordline group determined to have failed a first erase verify of an erase verify process, and causing a second erase verify of the erase verify process to be performed sequentially with respect to each failing wordline group of the set of failing wordline groups.

公开(公告)号：US20240176508A1

公开(公告)日：2024-05-30

申请号：US18521458

申请日：2023-11-28

Applicant: Micron Technology, Inc.

Inventor： Yu-Chung Lien ,  Zhongguang Xu ,  Ronit Roneel Prakash ,  Zhenming Zhou

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/0659 ,  G06F3/0679

Abstract: A system with a memory device and a processing device operatively coupled with the memory device, to perform operations including identifying a lifecycle state associated with a segment of the memory device, selecting, based on the lifecycle state, an erase policy for performing an erase operation with respect to the segment, and causing the erase operation to be performed with respect to the segment in accordance with the erase policy.

公开(公告)号：US11574690B2

公开(公告)日：2023-02-07

申请号：US17335132

申请日：2021-06-01

Applicant: Micron Technology, Inc.

Inventor： Ronit Roneel Prakash ,  Jiun-Horng Lai ,  Chengkuan Yin ,  Shinji Sato

IPC: G11C16/34 ,  G11C16/04

Abstract: A system includes a memory device including a memory array including a plurality of wordline groups and control logic, operatively coupled with the memory array, to perform operation including causing a first erase verify to be performed sequentially with respect to each wordline group of the plurality of wordline groups, identifying a set of failing wordline groups determined to have failed the first erase verify, and causing a second erase verify to be performed sequentially with respect to each wordline group of the set of failing wordline groups.

公开(公告)号：US20240281148A1

公开(公告)日：2024-08-22

申请号：US18443584

申请日：2024-02-16

Applicant: Micron Technology, Inc.

Inventor： Jiun-Horng Lai ,  Pitamber Shukla ,  Ching-Huang Lu ,  Chengkuan Yin ,  Ronit Roneel Prakash ,  Yoshiaki Fukuzumi

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/0659 ,  G06F3/0679

Abstract: Apparatuses, systems, and methods for determining a dynamic erase voltage step. One example apparatus can include an array of memory cells and a controller coupled to the array of memory cells, wherein the controller is configured to apply a first erase voltage to a first wordline and a second wordline in the array of memory cells to perform an erase operation, apply a first verify voltage to the first wordline to verify the erase operation, apply a second verify voltage greater than the first verify voltage to the second wordline in response to failing to verify the erase operation by applying the first verify voltage to the first wordline, and apply a second erase voltage to the first wordline and the second wordline in response to verifying the erase operation by applying the second verify voltage to the second wordline.

公开(公告)号：US20230197175A1

公开(公告)日：2023-06-22

申请号：US17994907

申请日：2022-11-28

Applicant: Micron Technology, Inc.

Inventor： Ronit Roneel Prakash ,  Ching-Huang Lu

IPC: G11C16/34 ,  G11C16/26 ,  G11C7/04

CPC classification number: G11C16/3459 ,  G11C16/26 ,  G11C7/04

Abstract: Control logic in a memory device receives a request to perform a memory access operation on a memory array of the memory device and determines an operating temperature of the memory device. The control logic further modifies a default magnitude of a source voltage signal based on the operating temperature to a form a modified source voltage signal, causes the modified source voltage signal to be applied to the memory array, and performs the memory access operation on the memory array.

公开(公告)号：US20240062827A1

公开(公告)日：2024-02-22

申请号：US18234289

申请日：2023-08-15

Applicant: Micron Technology, Inc.

Inventor： Ronit Roneel Prakash ,  Pitamber Shukla ,  Ching-Huang Lu ,  Murong Lang ,  Zhenming Zhou

IPC: G11C16/16 ,  G11C16/34 ,  G11C16/10 ,  G11C16/26

CPC classification number: G11C16/16 ,  G11C16/3445 ,  G11C16/102 ,  G11C16/26

Abstract: A memory device can include a memory device coupled with a processing device. The processing device causes a first erase operation to be performed at a block, where the first erase operation causes a pre-program voltage and a first erase voltage having a first magnitude to be applied to the block. The processing device causes an erase detection operation to be performed at the block. The processing device determines that the block fails to satisfy the erase detection operation responsive to causing the erase detection operation to be performed. The processing device further causes a second erase operation to be performed at the block responsive to determining that the block failed the erase detection operation, where the second erase operation causes a second erase voltage having a second magnitude to be applied to the block.

公开(公告)号：US20220383963A1

公开(公告)日：2022-12-01

申请号：US17335132

申请日：2021-06-01

Applicant: Micron Technology, Inc.

Inventor： Ronit Roneel Prakash ,  Jiun-Horng Lai ,  Chengkuan Yin ,  Shinji Sato

IPC: G11C16/34 ,  G11C16/04

Abstract: A system includes a memory device including a memory array including a plurality of wordline groups and control logic, operatively coupled with the memory array, to perform operation including causing a first erase verify to be performed sequentially with respect to each wordline group of the plurality of wordline groups, identifying a set of failing wordline groups determined to have failed the first erase verify, and causing a second erase verify to be performed sequentially with respect to each wordline group of the set of failing wordline groups.