公开(公告)号：US11646083B2

公开(公告)日：2023-05-09

申请号：US17868703

申请日：2022-07-19

Applicant: Micron Technology, Inc.

Inventor： Foroozan S. Koushan ,  Shinji Sato

IPC: G11C16/14 ,  G11C16/04 ,  G11C16/08 ,  G11C16/32

CPC classification number: G11C16/14 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/32

Abstract: Control logic in a memory device initiates an erase operation on a memory array and causes an erase voltage signal to be applied to a source terminal of a string of memory cells in a data block of the memory array during the erase operation. The control logic further causes a first voltage signal to be applied to a first select line of the data block and a second voltage signal to be applied to a second select line of the data block, wherein the first select line is coupled to a first device in the string of memory cells and the second select line is coupled to a second device in the string of memory cells, and wherein the first voltage signal and the second voltage signal both have a common first voltage offset with respect to the erase voltage signal during a first stage of the erase operation. The control logic further determines an end of the first stage of the erase operation and causes the first voltage signal to decrease to a second voltage offset with respect to the erase voltage signal and causes the second voltage signal to decrease to a third voltage offset with respect to the erase voltage signal during a second stage of the erase operation, wherein the second offset is greater than the third offset.

公开(公告)号：US20230040099A1

公开(公告)日：2023-02-09

申请号：US17971340

申请日：2022-10-21

Applicant: Micron Technology, Inc.

Inventor： Avinash Rajagiri ,  Shinji Sato

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/14 ,  G11C16/28

Abstract: A variety of applications can include memory devices designed to provide stabilization of selector devices in a memory array of the memory device. A selector stabilizer pulse can be applied to a selector device of a string of the memory array and to a memory cell of multiple memory cells of the string with the memory cell being adjacent to the selector device in the string. The selector stabilizer pulse can be applied directly following an erase operation to the string to stabilize the threshold voltage of the selector device. The selector stabilizer pulse can be applied as part of the erase algorithm of the memory device. Additional devices, systems, and methods are discussed.

公开(公告)号：US10354734B2

公开(公告)日：2019-07-16

申请号：US15911910

申请日：2018-03-05

Applicant: Micron Technology, Inc.

Inventor： Masanobu Saito ,  Shuji Tanaka ,  Shinji Sato

IPC: G11C16/06 ,  G11C16/14 ,  G11C16/26 ,  H01L27/11582 ,  H01L23/522 ,  H01L23/528 ,  G11C16/04 ,  G11C16/16 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  G11C16/10 ,  G11C16/30

Abstract: Some embodiments include apparatuses and methods of using and forming such apparatuses. An apparatus among the apparatuses includes first and second conductive materials located in respective first and second levels of the apparatus, a pillar including a length extending between the first and second conductive materials, memory cells and control lines located along the pillar, a first select gate and a first select line located along the pillar between the first conductive material and the memory cells, a second select gate and a second select line located along the pillar between the first conductive material and the first select line, a first transistor and a first transistor gate line located along the pillar between the first conductive material and the first select line, and a second transistor and a second transistor gate line located along the pillar between the first conductive material and the first transistor.

公开(公告)号：US11501842B2

公开(公告)日：2022-11-15

申请号：US16991535

申请日：2020-08-12

Applicant: Micron Technology, Inc.

Inventor： Avinash Rajagiri ,  Shinji Sato

IPC: G11C16/14 ,  G11C16/34 ,  G11C16/04 ,  G11C16/28

Abstract: A variety of applications can include memory devices designed to provide stabilization of selector devices in a memory array of the memory device. A selector stabilizer pulse can be applied to a selector device of a string of the memory array and to a memory cell of multiple memory cells of the string with the memory cell being adjacent to the selector device in the string. The selector stabilizer pulse can be applied directly following an erase operation to the string to stabilize the threshold voltage of the selector device. The selector stabilizer pulse can be applied as part of the erase algorithm of the memory device. Additional devices, systems, and methods are discussed.

公开(公告)号：US20220383963A1

公开(公告)日：2022-12-01

申请号：US17335132

申请日：2021-06-01

Applicant: Micron Technology, Inc.

Inventor： Ronit Roneel Prakash ,  Jiun-Horng Lai ,  Chengkuan Yin ,  Shinji Sato

IPC: G11C16/34 ,  G11C16/04

Abstract: A system includes a memory device including a memory array including a plurality of wordline groups and control logic, operatively coupled with the memory array, to perform operation including causing a first erase verify to be performed sequentially with respect to each wordline group of the plurality of wordline groups, identifying a set of failing wordline groups determined to have failed the first erase verify, and causing a second erase verify to be performed sequentially with respect to each wordline group of the set of failing wordline groups.

公开(公告)号：US11423990B2

公开(公告)日：2022-08-23

申请号：US16947642

申请日：2020-08-11

Applicant: Micron Technology, Inc.

Inventor： Foroozan S. Koushan ,  Shinji Sato

IPC: G11C16/14 ,  G11C16/04 ,  G11C16/08 ,  G11C16/32

Abstract: Control logic in a memory device initiates an erase operation on a memory array and causes an erase voltage signal to be applied to a source terminal of a string of memory cells in a data block of the memory array during the erase operation. The control logic further causes a first voltage signal to be applied to a first select line of the data block and a second voltage signal to be applied to a second select line of the data block, wherein the first select line is coupled to a first device in the string of memory cells and the second select line is coupled to a second device in the string of memory cells, and wherein the first voltage signal and the second voltage signal both have a common first voltage offset with respect to the erase voltage signal during a first stage of the erase operation. The control logic further determines an end of the first stage of the erase operation and causes the first voltage signal to decrease to a second voltage offset with respect to the erase voltage signal and causes the second voltage signal to decrease to a third voltage offset with respect to the erase voltage signal during a second stage of the erase operation, wherein the second offset is greater than the third offset.

公开(公告)号：US20180211710A1

公开(公告)日：2018-07-26

申请号：US15911910

申请日：2018-03-05

Applicant: Micron Technology, Inc.

Inventor： Masanobu Saito ,  Shuji Tanaka ,  Shinji Sato

IPC: G11C16/14 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11556 ,  G11C16/26 ,  H01L23/528 ,  H01L23/522 ,  H01L27/11524

CPC classification number: G11C16/14 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/30 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582

Abstract: Some embodiments include apparatuses and methods of using and forming such apparatuses. An apparatus among the apparatuses includes first and second conductive materials located in respective first and second levels of the apparatus, a pillar including a length extending between the first and second conductive materials, memory cells and control lines located along the pillar, a first select gate and a first select line located along the pillar between the first conductive material and the memory cells, a second select gate and a second select line located along the pillar between the first conductive material and the first select line, a first transistor and a first transistor gate line located along the pillar between the first conductive material and the first select line, and a second transistor and a second transistor gate line located along the pillar between the first conductive material and the first transistor.

公开(公告)号：US12002524B2

公开(公告)日：2024-06-04

申请号：US18085783

申请日：2022-12-21

Applicant: Micron Technology, Inc.

Inventor： Ronit Roneel Prakash ,  Jiun-Horng Lai ,  Chengkuan Yin ,  Shinji Sato

IPC: G11C16/34 ,  G11C16/04

CPC classification number: G11C16/3445 ,  G11C16/0483

Abstract: A memory device includes a memory array including a plurality of wordline groups, each wordline group of the plurality of wordline groups including a set of even wordlines and a set of odd wordlines, and control logic, operatively coupled with the memory array, to perform operations including identifying a set of failing wordline groups from the plurality of wordline groups, the set of failing wordline groups including at least one failing wordline group determined to have failed a first erase verify of an erase verify process, and causing a second erase verify of the erase verify process to be performed sequentially with respect to each failing wordline group of the set of failing wordline groups.

公开(公告)号：US11935604B2

公开(公告)日：2024-03-19

申请号：US17971340

申请日：2022-10-21

Applicant: Micron Technology, Inc.

Inventor： Avinash Rajagiri ,  Shinji Sato

IPC: G11C16/14 ,  G11C16/04 ,  G11C16/28 ,  G11C16/34

CPC classification number: G11C16/349 ,  G11C16/0433 ,  G11C16/0483 ,  G11C16/14 ,  G11C16/28 ,  G11C16/3404 ,  G11C16/3431 ,  G11C16/3445

Abstract: A variety of applications can include memory devices designed to provide stabilization of selector devices in a memory array of the memory device. A selector stabilizer pulse can be applied to a selector device of a string of the memory array and to a memory cell of multiple memory cells of the string with the memory cell being adjacent to the selector device in the string. The selector stabilizer pulse can be applied directly following an erase operation to the string to stabilize the threshold voltage of the selector device. The selector stabilizer pulse can be applied as part of the erase algorithm of the memory device. Additional devices, systems, and methods are discussed.

公开(公告)号：US20240028253A1

公开(公告)日：2024-01-25

申请号：US18224538

申请日：2023-07-20

Applicant: Micron Technology, Inc.

Inventor： Avinash Rajagiri ,  Ching-Huang Lu ,  Aman Gupta ,  Shuji Tanaka ,  Masashi Yoshida ,  Shinji Sato ,  Yingda Dong

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679

Abstract: A memory device can include a memory array coupled with a control logic. The control logic initiates a program operation on the memory array, the program operation including a program phase and a program recovery phase. The control logic causes a program voltage to be applied to a selected word line during the program phase. The control logic causes a select gate drain coupled with a string of memory cells to deactivate during the program recovery phase after applying the program voltage, where the string of memory cells include a plurality of memory cells each coupled to a corresponding word line of a plurality of wordlines. The control logic causes a voltage to be applied to a select gate source coupled with the string of memory cells to activate the select gate source during the program recovery phase concurrent to causing the select gate drain to deactivate.