公开(公告)号：US11574690B2

公开(公告)日：2023-02-07

申请号：US17335132

申请日：2021-06-01

Applicant: Micron Technology, Inc.

Inventor： Ronit Roneel Prakash ,  Jiun-Horng Lai ,  Chengkuan Yin ,  Shinji Sato

IPC: G11C16/34 ,  G11C16/04

Abstract: A system includes a memory device including a memory array including a plurality of wordline groups and control logic, operatively coupled with the memory array, to perform operation including causing a first erase verify to be performed sequentially with respect to each wordline group of the plurality of wordline groups, identifying a set of failing wordline groups determined to have failed the first erase verify, and causing a second erase verify to be performed sequentially with respect to each wordline group of the set of failing wordline groups.

公开(公告)号：US20220383963A1

公开(公告)日：2022-12-01

申请号：US17335132

申请日：2021-06-01

Applicant: Micron Technology, Inc.

Inventor： Ronit Roneel Prakash ,  Jiun-Horng Lai ,  Chengkuan Yin ,  Shinji Sato

IPC: G11C16/34 ,  G11C16/04

Abstract: A system includes a memory device including a memory array including a plurality of wordline groups and control logic, operatively coupled with the memory array, to perform operation including causing a first erase verify to be performed sequentially with respect to each wordline group of the plurality of wordline groups, identifying a set of failing wordline groups determined to have failed the first erase verify, and causing a second erase verify to be performed sequentially with respect to each wordline group of the set of failing wordline groups.

公开(公告)号：US20240281148A1

公开(公告)日：2024-08-22

申请号：US18443584

申请日：2024-02-16

Applicant: Micron Technology, Inc.

Inventor： Jiun-Horng Lai ,  Pitamber Shukla ,  Ching-Huang Lu ,  Chengkuan Yin ,  Ronit Roneel Prakash ,  Yoshiaki Fukuzumi

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/0659 ,  G06F3/0679

Abstract: Apparatuses, systems, and methods for determining a dynamic erase voltage step. One example apparatus can include an array of memory cells and a controller coupled to the array of memory cells, wherein the controller is configured to apply a first erase voltage to a first wordline and a second wordline in the array of memory cells to perform an erase operation, apply a first verify voltage to the first wordline to verify the erase operation, apply a second verify voltage greater than the first verify voltage to the second wordline in response to failing to verify the erase operation by applying the first verify voltage to the first wordline, and apply a second erase voltage to the first wordline and the second wordline in response to verifying the erase operation by applying the second verify voltage to the second wordline.

公开(公告)号：US12068036B2

公开(公告)日：2024-08-20

申请号：US17887765

申请日：2022-08-15

Applicant: Micron Technology, Inc.

Inventor： Jiun-horng Lai ,  Pitamber Shukla ,  Ching-Huang Lu ,  Chengkuan Yin ,  Yoshiaki Fukuzumi

IPC: G11C16/16 ,  G11C16/26 ,  G11C16/32

CPC classification number: G11C16/16 ,  G11C16/26 ,  G11C16/32

Abstract: A memory device includes a memory array comprising memory cells and control logic. The control logic performs operations including: causing a first erase pulse to be applied to a memory line of the memory array to perform an erase operation, the memory line being a conductive line coupled to a string of the memory cells; suspending the erase operation in response to receipt of a suspend command during a ramping period of the first erase pulse; recording a suspend voltage level of the first erase pulse when suspended; causing the erase operation to be resumed in response to an erase resume command; selectively modifying a pulse width of a flattop period of a second erase pulse based on the suspend voltage level; and causing the second erase pulse to be applied to the memory line during a resume of the erase operation.

公开(公告)号：US12002524B2

公开(公告)日：2024-06-04

申请号：US18085783

申请日：2022-12-21

Applicant: Micron Technology, Inc.

Inventor： Ronit Roneel Prakash ,  Jiun-Horng Lai ,  Chengkuan Yin ,  Shinji Sato

IPC: G11C16/34 ,  G11C16/04

CPC classification number: G11C16/3445 ,  G11C16/0483

Abstract: A memory device includes a memory array including a plurality of wordline groups, each wordline group of the plurality of wordline groups including a set of even wordlines and a set of odd wordlines, and control logic, operatively coupled with the memory array, to perform operations including identifying a set of failing wordline groups from the plurality of wordline groups, the set of failing wordline groups including at least one failing wordline group determined to have failed a first erase verify of an erase verify process, and causing a second erase verify of the erase verify process to be performed sequentially with respect to each failing wordline group of the set of failing wordline groups.

公开(公告)号：US20230402103A1

公开(公告)日：2023-12-14

申请号：US17887765

申请日：2022-08-15

Applicant: Micron Technology, Inc.

Inventor： Jiun-horng Lai ,  Pitamber Shukla ,  Ching-Huang Lu ,  Chengkuan Yin ,  Yoshiaki Fukuzumi

IPC: G11C16/16 ,  G11C16/26 ,  G11C16/32

CPC classification number: G11C16/16 ,  G11C16/26 ,  G11C16/32

Abstract: A memory device includes a memory array comprising memory cells and control logic. The control logic performs operations including: causing a first erase pulse to be applied to a memory line of the memory array to perform an erase operation, the memory line being a conductive line coupled to a string of the memory cells; suspending the erase operation in response to receipt of a suspend command during a ramping period of the first erase pulse; recording a suspend voltage level of the first erase pulse when suspended; causing the erase operation to be resumed in response to an erase resume command; selectively modifying a pulse width of a flattop period of a second erase pulse based on the suspend voltage level; and causing the second erase pulse to be applied to the memory line during a resume of the erase operation.

公开(公告)号：US20230117364A1

公开(公告)日：2023-04-20

申请号：US18085783

申请日：2022-12-21

Applicant: Micron Technology, Inc.

Inventor： Ronit Roneel Prakash ,  Jiun-Horng Lai ,  Chengkuan Yin ,  Shinji Sato

IPC: G11C16/34 ,  G11C16/04

Abstract: A memory device includes a memory array including a plurality of wordline groups, each wordline group of the plurality of wordline groups including a set of even wordlines and a set of odd wordlines, and control logic, operatively coupled with the memory array, to perform operations including identifying a set of failing wordline groups from the plurality of wordline groups, the set of failing wordline groups including at least one failing wordline group determined to have failed a first erase verify of an erase verify process, and causing a second erase verify of the erase verify process to be performed sequentially with respect to each failing wordline group of the set of failing wordline groups.