Invention Grant
- Patent Title: Serializer-deserializer die for high speed signal interconnect
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Application No.: US16117353Application Date: 2018-08-30
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Publication No.: US11581282B2Publication Date: 2023-02-14
- Inventor: Adel A. Elsherbini , Johanna M. Swan , Shawna M. Liff , Gerald S. Pasdast
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Akona IP PC
- Main IPC: H01L23/00
- IPC: H01L23/00 ; H01L23/48 ; H01L21/56 ; H03M9/00 ; H01L25/065 ; H01L25/00

Abstract:
In embodiments, a semiconductor package may include a first die and a second die. The package may additionally include a serializer/deserializer (SerDes) die coupled with the first and the second dies. The SerDes die may be configured to serialize signals transmitted from the first die to the second die, and deserialize signals received from the second die. Other embodiments may be described and/or claimed.
Public/Granted literature
- US20200075521A1 SERIALIZER-DESERIALIZER DIE FOR HIGH SPEED SIGNAL INTERCONNECT Public/Granted day:2020-03-05
Information query
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