公开(公告)号：US12129046B2

公开(公告)日：2024-10-29

申请号：US16866834

申请日：2020-05-05

申请人： Bell Textron Inc.

发明人： Phalgun Madhusudan

IPC分类号： B64D45/02 ,  B32B37/12 ,  B32B37/24 ,  B64C1/12 ,  C09D5/24 ,  C09K3/16

CPC分类号： B64D45/02 ,  B32B37/12 ,  B64C1/12 ,  C09D5/24 ,  C09K3/16 ,  B32B2037/243 ,  B32B2305/38 ,  B32B2311/00

摘要： According to one implementation of the present disclosure, a method is disclosed. The method includes forming one or more aircraft surfaces from at least one of one or more metal materials or metal composite materials; and forming a surface coating, at least partially covering the one or more aircraft surfaces, with one or more materials above a dielectric strength threshold.

公开(公告)号：US12126068B2

公开(公告)日：2024-10-22

申请号：US16912027

申请日：2020-06-25

申请人： Intel Corporation

发明人： Diego Correas-Serrano ,  Georgios Dogiamis ,  Henning Braunisch ,  Neelam Prabhu Gaunkar ,  Telesphor Kamgaing

IPC分类号： H01P3/16

CPC分类号： H01P3/16

摘要： Disclosed herein are components for millimeter-wave communication, as well as related methods and systems.

公开(公告)号：US12123205B2

公开(公告)日：2024-10-22

申请号：US17981777

申请日：2022-11-07

申请人： Canvas Construction, Inc.

发明人： Maria J. Telleria ,  Gabriel F. Hein ,  Kevin B. Albert ,  Thomas F. Allen ,  Charlie Yan

IPC分类号： E04F21/02 ,  B05B1/28 ,  B05B7/00 ,  B05B9/00 ,  B05B12/12 ,  B05B13/04 ,  B05B15/625 ,  B05C5/00 ,  B05C5/02 ,  B05C11/10 ,  B05D1/02 ,  B05D3/04 ,  B05D3/06 ,  B24B7/18 ,  B24B49/12 ,  B24B55/06 ,  B24B55/10 ,  B25J9/16 ,  B25J11/00 ,  B25J15/00 ,  B26D5/00 ,  E04B1/76 ,  E04F21/00 ,  E04F21/08 ,  E04F21/12 ,  E04F21/16 ,  E04F21/165 ,  E04F21/18 ,  B05B7/24 ,  B05B7/26 ,  B05B9/01 ,  B05B14/00 ,  B05C3/18 ,  B25J9/00 ,  B26D3/08

CPC分类号： E04F21/026 ,  B05B1/28 ,  B05B7/0093 ,  B05B9/007 ,  B05B12/122 ,  B05B13/0431 ,  B05B15/625 ,  B05C5/004 ,  B05C5/02 ,  B05C11/1039 ,  B05D1/02 ,  B05D3/0413 ,  B05D3/067 ,  B24B7/182 ,  B24B49/12 ,  B24B55/06 ,  B24B55/10 ,  B25J9/1661 ,  B25J9/1697 ,  B25J11/0055 ,  B25J11/0075 ,  B25J15/0019 ,  B26D5/007 ,  E04B1/7654 ,  E04F21/0046 ,  E04F21/08 ,  E04F21/085 ,  E04F21/12 ,  E04F21/16 ,  E04F21/165 ,  E04F21/1652 ,  E04F21/1657 ,  E04F21/18 ,  B05B7/24 ,  B05B7/26 ,  B05B9/01 ,  B05B14/00 ,  B05C3/18 ,  B25J9/0084 ,  B26D3/085 ,  G05B2219/40114 ,  G05B2219/40298 ,  Y10S901/01 ,  Y10S901/41 ,  Y10S901/43 ,  Y10S901/47

摘要： An automated drywalling system network that including one or more automated drywalling systems that each has a robotic arm. The automated drywalling system network can also include a computational planner that generates instructions for the one or more automated drywalling systems to perform two or more drywalling tasks associated with a target wall assembly. The two or more drywalling tasks can include a hanging task that includes hanging pieces of drywall on studs of the target wall assembly; a mudding task that includes applying joint compound to pieces of drywall hung on studs of the target wall assembly; a sanding task that includes sanding joint compound applied to the pieces of drywall hung on studs of the target wall assembly; and a painting task that includes painting sanded the joint compound applied to the pieces of drywall hung on studs of the target wall assembly.

公开(公告)号：US12119317B2

公开(公告)日：2024-10-15

申请号：US17032469

申请日：2020-09-25

申请人： Intel Corporation

发明人： Bhaskar Jyoti Krishnatreya ,  Nagatoshi Tsunoda ,  Shawna M. Liff ,  Sairam Agraharam

IPC分类号： H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/367 ,  H01L23/538 ,  H01L25/00 ,  H01L25/065

CPC分类号： H01L24/08 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/367 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/05 ,  H01L24/80 ,  H01L25/0652 ,  H01L25/50 ,  H01L2224/05147 ,  H01L2224/08145 ,  H01L2224/0823 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2225/06541 ,  H01L2225/06586

摘要： Disclosed herein are structures and techniques related to singulation of microelectronic components with direct bonding interfaces. For example, in some embodiments, a microelectronic component may include: a surface, wherein conductive contacts are at the surface; a trench at a perimeter of the surface; and a burr in the trench.

公开(公告)号：US12114479B2

公开(公告)日：2024-10-08

申请号：US17368329

申请日：2021-07-06

申请人： Intel Corporation

发明人： Wilfred Gomes ,  Mauro J. Kobrinsky ,  Abhishek A. Sharma ,  Rajesh Kumar ,  Kinyip Phoa ,  Elliot Tan ,  Tahir Ghani ,  Swaminathan Sivakumar

IPC分类号： H10B12/00 ,  G11C5/06 ,  H01L23/522 ,  H01L23/528 ,  H01L27/06 ,  H01L29/786

CPC分类号： H10B12/31 ,  G11C5/063 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/0688 ,  H01L29/78696 ,  H10B12/30

摘要： A three-dimensional memory array may include a first memory array and a second memory array, stacked above the first. Some memory cells of the first array may be coupled to a first layer selector transistor, while some memory cells of the second array may be coupled to a second layer selector transistor. The first and second layer selector transistor may be coupled to one another and to a peripheral circuit that controls operation of the first and/or second memory arrays. A different layer selector transistor may be used for each row of memory cells of a given memory array and/or for each column of memory cells of a given memory array. Such designs may allow increasing density of memory cells in a memory array having a given footprint area, or, conversely, reducing the footprint area of the memory array with a given memory cell density.

公开(公告)号：US12101475B2

公开(公告)日：2024-09-24

申请号：US17127544

申请日：2020-12-18

申请人： Intel Corporation

发明人： Brinda Ganesh ,  Nilesh Jain ,  Sumit Mohan ,  Faouzi Kossentini ,  Jill Boyce ,  James Holland ,  Zhijun Lei ,  Chekib Nouira ,  Foued Ben Amara ,  Hassene Tmar ,  Sebastian Possos ,  Craig Hurst

IPC分类号： H04N19/114 ,  H04N19/154

CPC分类号： H04N19/114 ,  H04N19/154

摘要： Techniques related to distributing the video encoding processing of an input video across hardware and software systems. Such techniques include evaluating the content of the video and determine whether or the encoding operation is best to be done on the hardware system only, software system only or a hybrid hardware and software system.

公开(公告)号：US12094822B2

公开(公告)日：2024-09-17

申请号：US16950240

申请日：2020-11-17

申请人： Intel Corporation

发明人： Guillaume Bouche ,  Andy Chih-Hung Wei ,  Changyok Park

IPC分类号： H01L23/528 ,  H01L21/768 ,  H01L21/8238 ,  H01L23/522 ,  H01L27/092 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L23/5286 ,  H01L21/76897 ,  H01L21/823821 ,  H01L21/823871 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/0924 ,  H01L29/0673 ,  H01L29/66795 ,  H01L29/785

摘要： Transistor arrangements fabricated by forming a metal gate cut as an opening that is non-selective to the gate sidewalls are disclosed. The etch process may be used to provide a power rail if the opening is at least partially filled with an electrically conductive material. Once an electrically conductive material has been deposited within the opening to form a power rail, recessing such a material in portions of the power rail that face gate stacks of various transistors may provide further improvements in terms of reduced parasitic capacitance. A mask for a trench contact to be used to electrically couple the power rail to a S/D region of a transistor may be used as a mask when the electrically conductive material of the power rail is recessed to realize a via that is self-aligned to the trench contact.

公开(公告)号：US12068525B2

公开(公告)日：2024-08-20

申请号：US17938768

申请日：2022-10-07

申请人： Intel Corporation

发明人： Sidharth Dalmia ,  Trang Thai

IPC分类号： H01Q1/22 ,  H01L23/66 ,  H01Q9/04 ,  H01Q21/06

CPC分类号： H01Q1/2283 ,  H01L23/66 ,  H01Q9/0407 ,  H01Q21/065 ,  H01L2223/6677 ,  H01L2924/1421 ,  H01L2924/15153 ,  H01L2924/15311

摘要： Disclosed herein are antenna boards, integrated circuit (IC) packages, antenna modules, and communication devices. For example, in some embodiments, an antenna module may include: an IC package having a die and a package substrate, and the package substrate has a recess therein; and an antenna patch, coupled to the package substrate, such that the antenna patch is over or at least partially in the recess.

公开(公告)号：US12068206B2

公开(公告)日：2024-08-20

申请号：US17030449

申请日：2020-09-24

申请人： Intel Corporation

发明人： Varun Mishra ,  Stephen M. Cea ,  Cory E. Weber ,  Jack T. Kavalieros ,  Tahir Ghani

IPC分类号： H01L23/00 ,  H01L21/84 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H10B51/10 ,  H10B51/30

CPC分类号： H01L21/845 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/78391 ,  H01L29/7853 ,  H10B51/10 ,  H10B51/30

摘要： Embodiments of the present disclosure are based on extending a nanocomb transistor architecture to implement gate all around, meaning that a gate enclosure of at least a gate dielectric material, or both a gate dielectric material and a gate electrode material, is provided on all sides of each nanoribbon of a vertical stack of lateral nanoribbons of a nanocomb transistor arrangement. In particular, extension of a nanocomb transistor architecture to implement gate all around, proposed herein, involves use of two dielectric wall materials which are etch-selective with respect to one another, instead of using only a single dielectric wall material used to implement conventional nanocomb transistor arrangements. Nanocomb-based transistor arrangements implementing gate all around as described herein may provide improvements in terms of the short-channel effects of conventional nanocomb transistor arrangements.

公开(公告)号：US12062551B2

公开(公告)日：2024-08-13

申请号：US18118835

申请日：2023-03-08

申请人： Intel Corporation

发明人： Sri Chaitra Jyotsna Chavali ,  Siddharth K. Alur ,  Lilia May ,  Amanda E. Schuckman

IPC分类号： H01L21/48 ,  H01L23/498

CPC分类号： H01L21/4857 ,  H01L23/49822 ,  H01L23/49827

摘要： Generally discussed herein are systems, devices, and methods that include an organic high density interconnect structure and techniques for making the same. According to an example a method can include forming one or more low density buildup layers on a core, conductive interconnect material of the one or more low density buildup layers electrically and mechanically connected to conductive interconnect material of the core, forming one or more high density buildup layers on an exposed low density buildup layer of the one or more low density buildup layers, conductive interconnect material of the high density buildup layers electrically and mechanically connected to the conductive interconnect material of the one or more low density buildup layers, and forming another low density buildup layer on and around an exposed high density buildup layer of the one or more high density buildup layers.