- Patent Title: Memory access techniques in memory devices with multiple partitions
-
Application No.: US17376716Application Date: 2021-07-15
-
Publication No.: US11586367B2Publication Date: 2023-02-21
- Inventor: Shekoufeh Qawami , Rajesh Sundaram
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Holland & Hart LLP
- Main IPC: G06F12/00
- IPC: G06F12/00 ; G06F13/00 ; G06F3/06 ; G11C13/00

Abstract:
Methods, systems, and devices for operating a memory array are described. A memory controller may be configured to provide enhanced bandwidth on a command/address (C/A) bus, which may have a relatively low pin count, through use of a next partition command that may repeat an array command from a current partition at a different partition indicated by the next partition command. Such a next partition command may use fewer clock cycles than a command that includes a complete instruction and memory location information.
Public/Granted literature
- US20220004329A1 MEMORY ACCESS TECHNIQUES IN MEMORY DEVICES WITH MULTIPLE PARTITIONS Public/Granted day:2022-01-06
Information query