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    TECHNIQUES TO UPDATE A TRIM PARAMETER IN NON-VOLATILE MEMORY
    1.
    发明申请
    TECHNIQUES TO UPDATE A TRIM PARAMETER IN NON-VOLATILE MEMORY 审中-公开

    公开(公告)号：US20200241751A1

    公开(公告)日：2020-07-30

    申请号：US16848608

    申请日：2020-04-14

    Applicant: Micron Technology, Inc.

    Inventor： Shekoufeh Qawami ,  Doyle W. Rivers

    IPC: G06F3/06

    Abstract: Techniques to update a trim parameter in non-volatile memory during either a manufacturing stage or a post-manufacturing stage are described. Trim parameters may be stored in a register located within the memory device that is inaccessible by a host device during a normal mode of operation. Post-manufacturing updates to trim parameters by the host device may be feasible by creating registers located within the memory device that are accessible to the host device to provide information regarding trim parameter setting updates. The memory device may read the information from the registers accessible to the host device to update trim parameters stored in the register inaccessible by the host device. In this manner, the host device may not have a direct access to the trim parameters but still be able to provide an update to the trim parameters by updating an entry of the registers accessible by the host device.

    Memory access techniques in memory devices with multiple partitions
    6.
    发明授权
    Memory access techniques in memory devices with multiple partitions 有权

    公开(公告)号：US11586367B2

    公开(公告)日：2023-02-21

    申请号：US17376716

    申请日：2021-07-15

    Applicant: Micron Technology, Inc.

    Inventor： Shekoufeh Qawami ,  Rajesh Sundaram

    IPC: G06F12/00 ,  G06F13/00 ,  G06F3/06 ,  G11C13/00

    Abstract: Methods, systems, and devices for operating a memory array are described. A memory controller may be configured to provide enhanced bandwidth on a command/address (C/A) bus, which may have a relatively low pin count, through use of a next partition command that may repeat an array command from a current partition at a different partition indicated by the next partition command. Such a next partition command may use fewer clock cycles than a command that includes a complete instruction and memory location information.

    TECHNIQUES TO UPDATE A TRIM PARAMETER IN NON-VOLATILE MEMORY
    7.
    发明申请
    TECHNIQUES TO UPDATE A TRIM PARAMETER IN NON-VOLATILE MEMORY 有权

    公开(公告)号：US20220057939A1

    公开(公告)日：2022-02-24

    申请号：US17518154

    申请日：2021-11-03

    Applicant: Micron Technology, Inc.

    Inventor： Shekoufeh Qawami ,  Doyle W. Rivers

    IPC: G06F3/06

    Abstract: Techniques to update a trim parameter in non-volatile memory during either a manufacturing stage or a post-manufacturing stage are described. Trim parameters may be stored in a register located within the memory device that is inaccessible by a host device during a normal mode of operation. Post-manufacturing updates to trim parameters by the host device may be feasible by creating registers located within the memory device that are accessible to the host device to provide information regarding trim parameter setting updates. The memory device may read the information from the registers accessible to the host device to update trim parameters stored in the register inaccessible by the host device. In this manner, the host device may not have a direct access to the trim parameters but still be able to provide an update to the trim parameters by updating an entry of the registers accessible by the host device.

    MEMORY ACCESS TECHNIQUES IN MEMORY DEVICES WITH MULTIPLE PARTITIONS
    8.
    发明申请
    MEMORY ACCESS TECHNIQUES IN MEMORY DEVICES WITH MULTIPLE PARTITIONS 有权

    公开(公告)号：US20220004329A1

    公开(公告)日：2022-01-06

    申请号：US17376716

    申请日：2021-07-15

    Applicant: Micron Technology, Inc.

    Inventor： Shekoufeh Qawami ,  Rajesh Sundaram

    IPC: G06F3/06 ,  G11C13/00

    Abstract: Methods, systems, and devices for operating a memory array are described. A memory controller may be configured to provide enhanced bandwidth on a command/address (C/A) bus, which may have a relatively low pin count, through use of a next partition command that may repeat an array command from a current partition at a different partition indicated by the next partition command. Such a next partition command may use fewer clock cycles than a command that includes a complete instruction and memory location information.

    Apparatuses and methods for adjusting write parameters based on a write count
    9.
    发明授权
    Apparatuses and methods for adjusting write parameters based on a write count 有权

    公开(公告)号：US11145369B2

    公开(公告)日：2021-10-12

    申请号：US16832061

    申请日：2020-03-27

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Shekoufeh Qawami ,  Rajesh Sundaram

    IPC: G06F12/08 ,  G11C14/00 ,  G11C13/00 ,  G11C16/10 ,  G11C16/34 ,  G11C7/24 ,  G11C8/18

    Abstract: According to one embodiment of the present invention, an apparatus is disclosed. The apparatus includes a memory array having a plurality of memory cells. The apparatus further includes memory access circuits coupled to the memory array and configured to perform write operations responsive to control signals. The apparatus further includes control logic coupled to the memory access circuits and configured to apply a set of write parameters based, at least in part, on a number of write operations performed by the memory access circuits and further configured to provide control signals to the memory access circuits to perform write operations on the plurality of memory cells according to the set of write parameters.

    Memory access techniques in memory devices with multiple partitions
    10.
    发明授权
    Memory access techniques in memory devices with multiple partitions 有权

    公开(公告)号：US11068183B2

    公开(公告)日：2021-07-20

    申请号：US16103697

    申请日：2018-08-14

    Applicant: Micron Technology, Inc.

    Inventor： Shekoufeh Qawami ,  Rajesh Sundaram

    IPC: G06F12/00 ,  G06F13/00 ,  G06F3/06 ,  G11C13/00

    Abstract: Methods, systems, and devices for operating a memory array are described. A memory controller may be configured to provide enhanced bandwidth on a command/address (C/A) bus, which may have a relatively low pin count, through use of a next partition command that may repeat an array command from a current partition at a different partition indicated by the next partition command. Such a next partition command may use fewer clock cycles than a command that includes a complete instruction and memory location information.

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