MEMORY ACCESS TECHNIQUES IN MEMORY DEVICES WITH MULTIPLE PARTITIONS

    公开(公告)号:US20190004729A1

    公开(公告)日:2019-01-03

    申请号:US16103697

    申请日:2018-08-14

    IPC分类号: G06F3/06

    摘要: Methods, systems, and devices for operating a memory array are described. A memory controller may be configured to provide enhanced bandwidth on a command/address (C/A) bus, which may have a relatively low pin count, through use of a next partition command that may repeat an array command from a current partition at a different partition indicated by the next partition command. Such a next partition command may use fewer clock cycles than a command that includes a complete instruction and memory location information.

    Devices, systems, and methods of reducing chip select

    公开(公告)号:US09996496B2

    公开(公告)日:2018-06-12

    申请号:US15685855

    申请日:2017-08-24

    摘要: Several systems and methods of chip select are described. In one such method, a device maintains two identifiers, (ID_a and ID_m). When the device receives a command, it examines the values of ID_a and ID_m relative to a third reference identifier (ID_s). If either ID_a or ID_m is equivalent to ID_s, the device executes the command, otherwise, the device ignores the command. By using two different identification methods, a system has options in choosing to activate devices, being able to selectively switch between selecting multiple devices and single devices in a quick manner. In another such method, a device may have a persistent area that stores identification information such as an ID_a. Thus, system functionality may remain independent from any defect/marginality associated with the physical or logical components required for initial ID_a assignment of all devices in the system.

    Devices, systems, and methods of reducing chip select
    4.
    发明授权
    Devices, systems, and methods of reducing chip select 有权
    减少芯片选择的设备,系统和方法

    公开(公告)号:US09477616B2

    公开(公告)日:2016-10-25

    申请号:US13961377

    申请日:2013-08-07

    IPC分类号: G06F13/14

    摘要: Several systems and methods of chip select are described. In one such method, a device maintains two identifiers, (ID_a and ID_m). When the device receives a command, it examines the values of ID_a and ID_m relative to a third reference identifier (ID_s). If either ID_a or ID_m is equivalent to ID_s, the device executes the command, otherwise, the device ignores the command. By using two different identification methods, a system has options in choosing to activate devices, being able to selectively switch between selecting multiple devices and single devices in a quick manner. In another such method, a device may have a persistent area that stores identification information such as an ID_a. Thus, system functionality may remain independent from any defect/marginality associated with the physical or logical components required for initial ID_a assignment of all devices in the system.

    摘要翻译: 描述了芯片选择的几种系统和方法。 在一种这样的方法中,设备维护两个标识符(ID_a和ID_m)。 当设备接收到命令时,它检查ID_a和ID_m相对于第三参考标识符(ID_s)的值。 如果ID_a或ID_m等于ID_s,则设备执行该命令,否则设备将忽略该命令。 通过使用两种不同的识别方法,系统具有选择激活设备的选项,能够以快速方式选择多个设备和单个设备之间进行选择性切换。 在另一种这样的方法中,设备可以具有存储诸如ID_a的标识信息的持久区域。 因此,系统功能可以独立于与系统中所有设备的初始ID_a分配所需的物理或逻辑组件相关联的任何缺陷/边际。

    DEVICES, SYSTEMS, AND METHODS OF REDUCING CHIP SELECT

    公开(公告)号:US20160328353A1

    公开(公告)日:2016-11-10

    申请号:US15212902

    申请日:2016-07-18

    IPC分类号: G06F13/42 G06F13/38

    摘要: Several systems and methods of chip select are described. In one such method, a device maintains two identifiers, (ID_a and ID_m). When the device receives a command, it examines the values of ID_a and ID_m relative to a third reference identifier (ID_s). If either ID_a or ID_m is equivalent to ID_s, the device executes the command, otherwise, the device ignores the command. By using two different identification methods, a system has options in choosing to activate devices, being able to selectively switch between selecting multiple devices and single devices in a quick manner. In another such method, a device may have a persistent area that stores identification information such as an ID_a. Thus, system functionality may remain independent from any defect/marginality associated with the physical or logical components required for initial ID_a assignment of all devices in the system.

    Devices, systems, and methods of reducing chip select

    公开(公告)号:US09785603B2

    公开(公告)日:2017-10-10

    申请号:US15212902

    申请日:2016-07-18

    摘要: Several systems and methods of chip select are described. In one such method, a device maintains two identifiers, (ID_a and ID_m). When the device receives a command, it examines the values of ID_a and ID_m relative to a third reference identifier (ID_s). If either ID_a or ID_m is equivalent to ID_s, the device executes the command, otherwise, the device ignores the command. By using two different identification methods, a system has options in choosing to activate devices, being able to selectively switch between selecting multiple devices and single devices in a quick manner. In another such method, a device may have a persistent area that stores identification information such as an ID_a. Thus, system functionality may remain independent from any defect/marginality associated with the physical or logical components required for initial ID_a assignment of all devices in the system.

    Apparatuses and methods for concurrently accessing multiple partitions of a non-volatile memory

    公开(公告)号:US11354040B2

    公开(公告)日:2022-06-07

    申请号:US16926431

    申请日:2020-07-10

    摘要: Apparatuses and methods for performing multithread, concurrent access of different partition of a memory are disclosed herein. An example apparatus may include a non-volatile memory array comprising a plurality of partitions. Each of the plurality of partitions may include a respective plurality of memory cells. The apparatus may further include a plurality of local controllers that are each configured to independently and concurrently access a respective one of the plurality of partitions to execute a respective memory access command of a plurality of memory access commands responsive to receiving the respective memory access command. The example apparatus may further include a controller configured to receive the plurality of memory access commands and to determine a respective target partition of the plurality of partitions for each of the plurality of memory access commands. The controller may be further configured to provide each of the plurality of memory access commands to a local controller of the plurality of local controllers associated with the respective target partition.