Invention Grant
- Patent Title: Multiple dies hardware processors and methods
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Application No.: US17513795Application Date: 2021-10-28
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Publication No.: US11586579B2Publication Date: 2023-02-21
- Inventor: Nevine Nassif , Yen-Cheng Liu , Krishnakanth V. Sistla , Gerald Pasdast , Siva Soumya Eachempati , Tejpal Singh , Ankush Varma , Mahesh K. Kumashikar , Srikanth Nimmagadda , Carleton L. Molnar , Vedaraman Geetha , Jeffrey D. Chamberlain , William R. Halleck , George Z. Chrysos , John R. Ayers , Dheeraj R. Subbareddy
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Nicholson De Vos Webster & Elliott LLP
- Main IPC: G06F1/04
- IPC: G06F1/04 ; G06F1/12 ; G06F15/78 ; G06F1/10 ; G06F15/167 ; G06F9/38 ; G06F9/50 ; G06F15/173

Abstract:
Methods and apparatuses relating to hardware processors with multiple interconnected dies are described. In one embodiment, a hardware processor includes a plurality of physically separate dies, and an interconnect to electrically couple the plurality of physically separate dies together. In another embodiment, a method to create a hardware processor includes providing a plurality of physically separate dies, and electrically coupling the plurality of physically separate dies together with an interconnect.
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