Invention Grant
- Patent Title: Resistive memory array
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Application No.: US17104405Application Date: 2020-11-25
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Publication No.: US11588103B2Publication Date: 2023-02-21
- Inventor: Youngseok Kim , Choonghyun Lee , Timothy Mathew Philip , Soon-Cheon Seo , Injo Ok , Alexander Reznicek
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agent Matthew Zehrer
- Main IPC: H01L45/00
- IPC: H01L45/00 ; H01L27/24

Abstract:
A vertical resistive memory array is presented. The array includes a pillar electrode and a switching liner around the side perimeter of the pillar electrode. The array includes two or more vertically stacked single cell (SC) electrodes connected to a first side of the switching liner. The juxtaposition of the switching liner, the pillar electrode, and each SC electrode forms respective resistance switching cells (e.g., OxRRAM cell). A vertical group or bank of these cells may be connected in parallel and each share the same pillar electrode. The cells in the vertical cell bank may written to or read from as a group to limit the effects of inconsistent CF formation of any one or more individual cells within the group.
Public/Granted literature
- US20220165947A1 RESISTIVE MEMORY ARRAY Public/Granted day:2022-05-26
Information query
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