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    Resistive memory array
    1.
    发明授权
    Resistive memory array 有权

    公开(公告)号：US11588103B2

    公开(公告)日：2023-02-21

    申请号：US17104405

    申请日：2020-11-25

    申请人： International Business Machines Corporation

    发明人： Youngseok Kim ,  Choonghyun Lee ,  Timothy Mathew Philip ,  Soon-Cheon Seo ,  Injo Ok ,  Alexander Reznicek

    IPC分类号： H01L45/00 ,  H01L27/24

    摘要： A vertical resistive memory array is presented. The array includes a pillar electrode and a switching liner around the side perimeter of the pillar electrode. The array includes two or more vertically stacked single cell (SC) electrodes connected to a first side of the switching liner. The juxtaposition of the switching liner, the pillar electrode, and each SC electrode forms respective resistance switching cells (e.g., OxRRAM cell). A vertical group or bank of these cells may be connected in parallel and each share the same pillar electrode. The cells in the vertical cell bank may written to or read from as a group to limit the effects of inconsistent CF formation of any one or more individual cells within the group.

    BACK END OF LINE EMBEDDED RRAM STRUCTURE WITH LOW FORMING VOLTAGE
    2.
    发明申请
    BACK END OF LINE EMBEDDED RRAM STRUCTURE WITH LOW FORMING VOLTAGE 有权

    公开(公告)号：US20230051052A1

    公开(公告)日：2023-02-16

    申请号：US17444841

    申请日：2021-08-11

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： Oleg Gluschenkov ,  Alexander Reznicek ,  Youngseok Kim ,  Injo Ok ,  Soon-Cheon Seo

    IPC分类号： H01L45/00 ,  H01L27/24

    摘要： A semiconductor structure may include a resistive random access memory device embedded between an upper metal interconnect and a lower metal interconnect in a backend structure of a chip. The resistive random access memory may include a first electrode and a second electrode separated by a dielectric film. A portion of the dielectric film directly above the first electrode may be crystalline. The semiconductor structure may include a stud below and in electrical contact with the first electrode and the lower metal interconnect and a dielectric layer between the upper metal interconnect and the lower metal interconnect. The dielectric layer may separate the upper metal interconnect from the lower metal interconnect. The crystalline portion of the dielectric film may include grain boundaries that extend through an entire thickness of the dielectric film. The crystalline portion of the dielectric film may include grains.

    SETTING AN UPPER BOUND ON RRAM RESISTANCE
    3.
    发明申请
    SETTING AN UPPER BOUND ON RRAM RESISTANCE 有权

    公开(公告)号：US20220223205A1

    公开(公告)日：2022-07-14

    申请号：US17147401

    申请日：2021-01-12

    申请人： International Business Machines Corporation

    发明人： Youngseok Kim ,  Soon-Cheon Seo ,  Choonghyun Lee ,  Injo Ok ,  Alexander Reznicek

    IPC分类号： G11C13/00 ,  H01L45/00

    摘要： An electronic circuit includes a plurality of word lines; a plurality of bit lines intersecting the plurality of word lines at a plurality of grid points; and a plurality of resistive random-access memory cells located at the plurality of grid points. Each of the resistive random-access memory cells includes a top metal coupled to one of: a corresponding one of the word lines and a corresponding one of the bit lines; a bottom metal coupled to another one of: the corresponding one of the word lines and the corresponding one of the bit lines; a dielectric sandwiched between the top metal and the bottom metal; and a high-resistance semiconductive spacer electrically connecting the top metal and the bottom metal in parallel with the dielectric.

    RESISTIVE MEMORY ARRAY
    5.
    发明申请
    RESISTIVE MEMORY ARRAY 有权

    公开(公告)号：US20220165947A1

    公开(公告)日：2022-05-26

    申请号：US17104405

    申请日：2020-11-25

    申请人： International Business Machines Corporation

    发明人： Youngseok Kim ,  Choonghyun Lee ,  Timothy Mathew Philip ,  Soon-Cheon Seo ,  Injo Ok ,  Alexander Reznicek

    IPC分类号： H01L45/00 ,  H01L27/24

    摘要： A vertical resistive memory array is presented. The array includes a pillar electrode and a switching liner around the side perimeter of the pillar electrode. The array includes two or more vertically stacked single cell (SC) electrodes connected to a first side of the switching liner. The juxtaposition of the switching liner, the pillar electrode, and each SC electrode forms respective resistance switching cells (e.g., OxRRAM cell). A vertical group or bank of these cells may be connected in parallel and each share the same pillar electrode. The cells in the vertical cell bank may written to or read from as a group to limit the effects of inconsistent CF formation of any one or more individual cells within the group.

    Source and drain isolation for CMOS nanosheet with one block mask
    9.
    发明授权
    Source and drain isolation for CMOS nanosheet with one block mask 有权

    公开(公告)号：US10804165B2

    公开(公告)日：2020-10-13

    申请号：US16440095

    申请日：2019-06-13

    申请人： International Business Machines Corporation

    发明人： Soon-Cheon Seo ,  Choonghyun Lee ,  Injo Ok

    IPC分类号： H01L21/70 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/66 ,  H01L29/165 ,  H01L27/092 ,  H01L29/786 ,  H01L29/423 ,  H01L29/775 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78

    摘要： Techniques for source/drain isolation in nanosheet devices are provided. In one aspect, a method of forming a nanosheet device includes: forming an alternating series of sacrificial/active channel nanosheets as a stack on a substrate; forming gates on the stack; forming spacers alongside opposite sidewalls of the gates; patterning the stack, in between the spacers, into individual PFET/NFET stacks and pockets in the substrate; laterally recessing the sacrificial nanosheets in the PFET/NFET stacks to expose tips of the active channel nanosheets in the PFET/NFET stacks; forming inner spacers alongside the PFET/NFET stacks covering the tips of the active channel nanosheets; forming a protective layer lining the pockets; and selectively etching back the inner spacers to expose tips of the active channel nanosheets and epitaxially growing source and drains from the exposed tips of the active channel nanosheets sequentially in the PFET/NFET stacks. A nanosheet device is also provided.