Invention Grant
- Patent Title: Low-capacitance structures and processes
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Application No.: US17353089Application Date: 2021-06-21
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Publication No.: US11605736B2Publication Date: 2023-03-14
- Inventor: Jia-Chuan You , Chia-Hao Chang , Tien-Lu Lin , Yu-Ming Lin , Chih-Hao Wang
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L29/76
- IPC: H01L29/76 ; H01L29/78 ; H01L29/66 ; H01L29/417

Abstract:
Semiconductor devices and methods of forming the same are provided. In one embodiment, a semiconductor device includes a fin extending from a substrate, a gate structure over a channel region of the fin, a source/drain contact over a source/drain region of the fin, a spacer extending along a sidewall of the gate structure, a liner extending along a sidewall of the source/drain contact, a gate contact via over and electrically coupled to the gate structure, and a source/drain contact via over and electrically coupled to the source/drain contact. The gate contact via extends through a first dielectric layer such that a portion of the first dielectric layer interposes between the gate contact via and the spacer. The source/drain contact via extends through a second dielectric layer such that a portion of the second dielectric layer interposes between the source/drain contact via and the liner.
Public/Granted literature
- US20210313464A1 LOW-CAPACITANCE STRUCTURES AND PROCESSES Public/Granted day:2021-10-07
Information query
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