公开(公告)号：US12256550B2

公开(公告)日：2025-03-18

申请号：US18327439

申请日：2023-06-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bo-Feng Young ,  Meng-Han Lin ,  Chih-Yu Chang ,  Sai-Hooi Yeong ,  Yu-Ming Lin

IPC: H10B51/20 ,  H01L21/02 ,  H01L23/522 ,  H01L29/24 ,  H10B51/30

Abstract: A memory cell includes patterning a first trench extending through a first conductive line, depositing a memory film along sidewalls and a bottom surface of the first trench, depositing a channel layer over the memory film, the channel layer extending along the sidewalls and the bottom surface of the first trench, depositing a first dielectric layer over and contacting the channel layer to fill the first trench, patterning a first opening, wherein patterning the first opening comprises etching the first dielectric layer, depositing a gate dielectric layer in the first opening, and depositing a gate electrode over the gate dielectric layer and in the first opening, the gate electrode being surrounded by the gate dielectric layer.

公开(公告)号：US20250072002A1

公开(公告)日：2025-02-27

申请号：US18941445

申请日：2024-11-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bo-Feng Young ,  Sai-Hooi Yeong ,  Yu-Ming Lin ,  Chi On Chui

IPC: H10B51/20 ,  H01L29/786 ,  H10B51/10 ,  H10B53/20

Abstract: A memory cell includes a thin film transistor over a semiconductor substrate. The thin film transistor includes a memory film contacting a word line, an oxide semiconductor (OS) layer contacting a source line and a bit line, and a conductive feature interposed between the memory film and the OS layer. The memory film is disposed between the OS layer and the word line. A dielectric material covers sidewalls of the source line, the memory film, and the OS layer.

公开(公告)号：US12170245B2

公开(公告)日：2024-12-17

申请号：US17871029

申请日：2022-07-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Zhen Yu ,  Chia-Hao Chang ,  Cheng-Chi Chuang ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L23/522 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/528 ,  H01L27/088

Abstract: A method includes providing a semiconductor structure having a metal gate structure (MG), gate spacers disposed on sidewalls of the MG, and a source/drain (S/D) feature disposed adjacent to the gate spacers; forming a first metal layer over the S/D feature and between the gate spacers; recessing the first metal layer to form a trench; forming a dielectric layer on sidewalls of the trench; forming a second metal layer over the first metal layer in the trench, wherein sidewalls of the second metal layer are defined by the dielectric layer; and forming a contact feature over the MG to contact the MG.

公开(公告)号：US12167608B2

公开(公告)日：2024-12-10

申请号：US17981608

申请日：2022-11-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Han-Jong Chia ,  Sheng-Chen Wang ,  Feng-Cheng Yang ,  Yu-Ming Lin ,  Chung-Te Lin

IPC: H10B51/20 ,  G11C11/22 ,  H01L23/522 ,  H01L29/66 ,  H01L29/78 ,  H10B43/20 ,  H10B43/27 ,  H10B51/10 ,  H10B51/30

Abstract: In an embodiment, a device includes: a source line extending in a first direction; a bit line extending in the first direction; a back gate between the source line and the bit line, the back gate extending in the first direction; a channel layer surrounding the back gate; a word line extending in a second direction, the second direction perpendicular to the first direction; and a data storage layer extending along the word line, the data storage layer between the word line and the channel layer, the data storage layer between the word line and the bit line, the data storage layer between the word line and the source line.

公开(公告)号：US20240379408A1

公开(公告)日：2024-11-14

申请号：US18783905

申请日：2024-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lin-Yu Huang ,  Sheng-Tsung Wang ,  Chia-Hao Chang ,  Tien-Lu Lin ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L21/762 ,  H01L21/311 ,  H01L27/088

Abstract: A method and structure directed to providing a source/drain isolation structure includes providing a device having a first source/drain region adjacent to a second source/drain region. A masking layer is deposited between the first and second source/drain regions and over an exposed first part of the second source/drain region. After depositing the masking layer, a first portion of an ILD layer disposed on either side of the masking layer is etched, without substantial etching of the masking layer, to expose a second part of the second source/drain region and to expose the first source/drain region. After etching the first portion of the ILD layer, the masking layer is etched to form an L-shaped masking layer. After forming the L-shaped masking layer, a first metal layer is formed over the exposed first source/drain region and a second metal layer is formed over the exposed second part of the second source/drain region.

公开(公告)号：US20240363757A1

公开(公告)日：2024-10-31

申请号：US18770865

申请日：2024-07-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Zhen Yu ,  Jia-Chuan You ,  Chia-Hao Chang ,  Tien-Lu Lin ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L29/78 ,  H01L21/02 ,  H01L27/088 ,  H01L29/66

CPC classification number: H01L29/7851 ,  H01L21/02381 ,  H01L21/02532 ,  H01L27/0886 ,  H01L29/66795 ,  H01L29/7848

Abstract: A method includes providing a semiconductor structure having metal gate structures (MGs), gate spacers disposed on sidewalls of the MGs, and source/drain (S/D) features disposed adjacent to the gate spacers; forming a first dielectric layer over the MGs and forming S/D contacts (MDs) over the S/D features; forming a second dielectric layer over the first dielectric layer, where portions of the second dielectric layer contact the MDs and the second dielectric layer is different from the first dielectric layer in composition; removing the portions of the second dielectric layer that contact the MDs; forming a conductive layer over the MDs and over the first dielectric layer; and removing portions of the conductive layer to form conductive features over the MDs.

公开(公告)号：US20240347625A1

公开(公告)日：2024-10-17

申请号：US18752172

申请日：2024-06-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Chi Chuang ,  Lin-Yu Huang ,  Chia-Hao Chang ,  Yu-Ming Lin ,  Ting-Ya Lo ,  Chi-Lin Teng ,  Hsin-Yen Huang ,  Hai-Ching Chen

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/49 ,  H01L29/78

CPC classification number: H01L29/6656 ,  H01L21/823468 ,  H01L29/4991 ,  H01L29/6653 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor structure includes a substrate, a semiconductor layer, a gate stack, two first gate spacers over two opposing sidewalls of the gate stack and extending above the gate stack; a second gate spacer over a sidewall of one of the first gate spacers and having an upper portion over a lower portion; an etch stop layer adjacent to the lower portion and spaced away from the upper portion; and a seal layer over the gate stack, the two first gate spacers and the second gate spacer, resulting in a first void and a second void below the first seal layer. The first void is above the lower portion of the second gate spacer and laterally between the etch stop layer and the upper portion of the second gate spacer. The second void is above the gate stack and laterally between the two first gate spacers.

公开(公告)号：US20240322041A1

公开(公告)日：2024-09-26

申请号：US18674634

申请日：2024-05-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Huan-Chieh Su ,  Chih-Hao Wang ,  Kuo-Cheng Chiang ,  Wei-Hao Wu ,  Zhi-Chang Lin ,  Jia-Ni Yu ,  Yu-Ming Lin ,  Chung-Wei Hsu

IPC: H01L29/78 ,  H01L21/768 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L21/76829 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823864 ,  H01L27/0924 ,  H01L29/66795

Abstract: A semiconductor device includes a semiconductor layer. A gate structure is disposed over the semiconductor layer. A spacer is disposed on a sidewall of the gate structure. A height of the spacer is greater than a height of the gate structure. A liner is disposed on the gate structure and on the spacer. The spacer and the liner have different material compositions.

公开(公告)号：US12069865B2

公开(公告)日：2024-08-20

申请号：US17567586

申请日：2022-01-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bo-Feng Young ,  Sai-Hooi Yeong ,  Chi On Chui ,  Yu-Ming Lin

IPC: H01L51/30 ,  H01L21/02 ,  H01L21/768 ,  H01L29/06 ,  H01L29/24 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786 ,  H10B43/20 ,  H10B43/30 ,  H10B51/20 ,  H10B51/30 ,  H10B99/00

CPC classification number: H10B51/30 ,  H01L21/02565 ,  H01L21/02603 ,  H01L21/76816 ,  H01L21/76877 ,  H01L29/0673 ,  H01L29/24 ,  H01L29/42392 ,  H01L29/66969 ,  H01L29/78391 ,  H01L29/78696 ,  H10B43/20 ,  H10B43/30 ,  H10B51/20 ,  H10B99/00

Abstract: 3D-NOR memory array devices and methods of manufacture are disclosed herein. A method includes forming a multi-layer stack over a substrate by forming alternating layers of an isolation material and a dummy material. An array of dummy nanostructures is formed in a channel region of the multi-layer stack by performing a wire release process. Once the nanostructures have been formed, a single layer of an oxide semiconductor material is deposited over and surrounds the dummy nanostructures. A memory film is then deposited over the oxide semiconductor material and a conductive wrap-around structure is formed over the memory film. Source/bit line structures may be formed by replacing the layers of the dummy material outside of the channel region with a metal fill material. A staircase conductor structure can be formed the source/bit line structures in a region of the multi-layer stack adjacent the memory array.

公开(公告)号：US20240268128A1

公开(公告)日：2024-08-08

申请号：US18637552

申请日：2024-04-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Chih-Yu Chang ,  Han-Jong Chia ,  Sai-Hooi Yeong ,  Yu-Ming Lin

IPC: H10B63/00 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8234 ,  H01L27/06 ,  H01L29/06 ,  H01L29/24 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786 ,  H01L29/861 ,  H10B43/20 ,  H10B43/35 ,  H10N70/00 ,  H10N70/20

CPC classification number: H10B63/84 ,  H01L21/02565 ,  H01L21/8221 ,  H01L21/823475 ,  H01L27/0688 ,  H01L29/0673 ,  H01L29/24 ,  H01L29/42392 ,  H01L29/66969 ,  H01L29/78696 ,  H01L29/861 ,  H10B43/20 ,  H10B63/20 ,  H10B63/30 ,  H10N70/011 ,  H10B43/35 ,  H10N70/20

Abstract: Memory devices and methods of forming the memory devices are disclosed herein. The memory devices include a resistive memory array including a first resistive memory cell, a staircase contact structure adjacent the resistive memory array, and an inter-metal dielectric layer over the staircase contact structure. The memory devices further include a first diode and a second diode over the inter-metal dielectric layer. The memory devices further include a first conductive via electrically coupling the first diode to a first resistor of the first resistive memory cell and a second conductive via electrically coupling the second diode to a second resistor of the first resistive memory cell.