- 专利标题: Method and system for latch-up prevention
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申请号: US17129195申请日: 2020-12-21
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公开(公告)号: US11615227B2公开(公告)日: 2023-03-28
- 发明人: Po-Chia Lai , Kuo-Ji Chen , Wen-Hao Chen , Wun-Jie Lin , Yu-Ti Su , Rabiul Islam , Shu-Yi Ying , Stefan Rusu , Kuan-Te Li , David Barry Scott
- 申请人: Taiwan Semiconductor Manufacturing Company, Ltd.
- 申请人地址: TW Hsinchu
- 专利权人: Taiwan Semiconductor Manufacturing Company, Ltd.
- 当前专利权人: Taiwan Semiconductor Manufacturing Company, Ltd.
- 当前专利权人地址: TW Hsinchu
- 代理机构: Merchant & Gould PC
- 主分类号: G06F30/30
- IPC分类号: G06F30/30 ; G06F30/392 ; H01L27/02 ; G01R31/50 ; G06F30/327 ; G06F30/367 ; G06F30/398 ; G06F117/02
摘要:
An integrated circuit design method includes receiving an integrated circuit design, and determining a floor plan for the integrated circuit design. The floor plan includes an arrangement of a plurality of functional cells and a plurality of tap cells. Potential latchup locations in the floor plan are determined, and the arrangement of at least one of the functional cells or the tap cells is modified based on the determined potential latchup locations.
公开/授权文献
- US20210117605A1 METHOD AND SYSTEM FOR LATCH-UP PREVENTION 公开/授权日:2021-04-22
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