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公开(公告)号：US20240176944A1
公开(公告)日：2024-05-30
申请号：US18434345
申请日：2024-02-06
发明人： Hung-Chih Ou , Kuo-Fu Lee , Wen-Hao Chen , Keh-Jeng Chang , Hsiang-Ho Chang
IPC分类号： G06F30/398 , G06F119/18
CPC分类号： G06F30/398 , G06F2119/18
摘要： A method of process technology assessment is provided. The method includes: defining a scope of the process technology assessment, the scope comprising an original process technology and a first process technology; modeling a first object in an integrated circuit into a resistance domain and a capacitance domain; generating a first resistance scaling factor and a first capacitance scaling factor based on the modeling, the original process technology, and the first process technology; and utilizing, by an electronic design automation (EDA) tool, the first resistance scaling factor and the first capacitance scaling factor for simulation of the integrated circuit.
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公开(公告)号：US11727185B2
公开(公告)日：2023-08-15
申请号：US17815013
申请日：2022-07-26
IPC分类号： G06F30/394 , G06F30/20 , G06F30/327 , G06F30/392 , G06F30/3312 , G06F30/373 , G06F30/33 , G06F30/337 , G06F30/398 , H01L23/52 , H01L23/522 , G06F111/04 , G06F119/12
CPC分类号： G06F30/394 , G06F30/20 , G06F30/327 , G06F30/3312 , G06F30/392 , G06F30/33 , G06F30/337 , G06F30/373 , G06F30/398 , G06F2111/04 , G06F2119/12 , H01L23/5226
摘要： A system includes a non-transitory computer readable medium configured to store instructions thereon. The system further includes a processor connected to the non-transitory computer readable medium. The processor is configured to execute the instruction for comparing a size of a via pillar structure of a first layout pattern of a plurality of layout patterns with a size of a via pillar structure of a second layout pattern of the plurality of layout patterns, wherein each of the plurality of layout patterns meets an electromigration (EM) rule. The processor is further configured to execute the instructions for replacing, in a layout design, the first layout pattern with the second layout pattern in response to the size of the via pillar structure of the second layout pattern being less than the size of the via pillar structure of the first layout pattern.
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公开(公告)号：US10678991B2
公开(公告)日：2020-06-09
申请号：US16020132
申请日：2018-06-27
发明人： Chun-Yao Ku , Wen-Hao Chen , Ming-Tao Yu , Shao-Huan Wang , Jyun-Hao Chang
IPC分类号： G06F17/50 , G06F30/398 , G06F30/394 , G06F119/10
摘要： A method of forming an integrated device includes: pre-storing a plurality of via pillars in a storage tool; arranging a first via pillar selected from the plurality of via pillars to electrically connect to a circuit cell in a first circuit; analyzing electromigration (EM) information of the first circuit to determine if the first via pillar induces an EM phenomenon; arranging a second via pillar selected from the plurality of via pillars to replace the first via pillar of the circuit cell to generate a second circuit when the first via pillar induces the EM phenomenon; and generating the integrated device according to the second circuit.
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公开(公告)号：US20200019666A1
公开(公告)日：2020-01-16
申请号：US16263841
申请日：2019-01-31
发明人： Po-Chia Lai , Kuo-Ji Chen , Wen-Hao Chen , Wun-Jie Lin , Yu-Ti Su , Rabiul Islam , Shu-Yi Ying , Stefan Rusu , Kuan-Te Li , David Barry Scott
摘要： An integrated circuit design method includes receiving an integrated circuit design, and determining a floor plan for the integrated circuit design. The floor plan includes an arrangement of a plurality of functional cells and a plurality of tap cells. Potential latchup locations in the floor plan are determined, and the arrangement of at least one of the functional cells or the tap cells is modified based on the determined potential latchup locations.
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公开(公告)号：US10360342B2
公开(公告)日：2019-07-23
申请号：US15704654
申请日：2017-09-14
发明人： Hung-Chih Ou , Chun-Yao Ku , Wen-Hao Chen
摘要： A method performed by at least one processor includes: accessing a layout of an integrated circuit (IC), where the layout comprises a first cell coupled to a metallization unit and the metallization unit includes one of a first via pillar (VP) structure and a single-via stacking structure; determining whether the layout meets a timing constraint; and performing, in response to the layout being determined as failing the timing constraint, an engineering change order (ECO) operation by replacing the metallization unit with a second VP structure.
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公开(公告)号：US09977857B1
公开(公告)日：2018-05-22
申请号：US15600410
申请日：2017-05-19
发明人： Chun-Yao Ku , Hung-Chih Ou , Shao-Huan Wang , Wen-Hao Chen , Ming-Tao Yu
IPC分类号： H01L21/82 , G06F17/50 , H01L23/522
CPC分类号： G06F17/5081 , G06F17/5077 , H01L23/5226
摘要： In examples described herein, methods for via pillar placement and an integrated circuit design including a via pillar are described. In some instances, a path within an integrated circuit or proposed integrated circuit design can be identified as having negative slack. In such instances, in particular where the path includes a fanout to input pins of receivers, a via pillar can be inserted at a location prior to fanout of the path. The via pillar can be inserted, for example, proximate to the fanout, but between the fanout and an output pin of a driver that is connected to the path.
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公开(公告)号：US20240039518A1
公开(公告)日：2024-02-01
申请号：US17873952
申请日：2022-07-26
发明人： Hung-Chih Ou , Wen-Hao Chen
摘要： A device including a first supply voltage track, a second supply voltage track, a first reference track, a first standard cell, and a second standard cell. The first supply voltage track is configured to provide a first voltage and the second supply voltage track is configured to provide a second voltage that is greater than the first voltage. The first standard cell is configured to be electrically connected to the first supply voltage track to receive the first voltage and electrically connected to the first reference track. The second standard cell is configured to be electrically connected to the second supply voltage track to receive the second voltage and electrically connected to the first reference track.
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公开(公告)号：US11681853B2
公开(公告)日：2023-06-20
申请号：US17692767
申请日：2022-03-11
发明人： Sheng-Hsiung Chen , Wen-Hao Chen , Hung-Chih Ou , Chun-Yao Ku , Shao-Huan Wang
IPC分类号： G06F30/30 , G06F30/398 , G06F30/3315 , G06F30/337 , G06F30/396 , G06F115/06 , G06F119/06 , G06F119/12 , G06F30/392
CPC分类号： G06F30/398 , G06F30/337 , G06F30/3315 , G06F30/396 , G06F30/392 , G06F2115/06 , G06F2119/06 , G06F2119/12
摘要： A multi-bit flip-flop includes a first flip-flop, a second flip-flop and a first inverter. The first flip-flop has a first driving capability. The second flip-flop has a second driving capability different from the first driving capability. The first inverter is configured to receive a first clock signal on a first clock pin, and is configured to generate a second clock signal inverted from the first clock signal. The first flip-flop and the second flip-flop are configured to share at least the first clock pin.
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公开(公告)号：US11615227B2
公开(公告)日：2023-03-28
申请号：US17129195
申请日：2020-12-21
发明人： Po-Chia Lai , Kuo-Ji Chen , Wen-Hao Chen , Wun-Jie Lin , Yu-Ti Su , Rabiul Islam , Shu-Yi Ying , Stefan Rusu , Kuan-Te Li , David Barry Scott
IPC分类号： G06F30/30 , G06F30/392 , H01L27/02 , G01R31/50 , G06F30/327 , G06F30/367 , G06F30/398 , G06F117/02
摘要： An integrated circuit design method includes receiving an integrated circuit design, and determining a floor plan for the integrated circuit design. The floor plan includes an arrangement of a plurality of functional cells and a plurality of tap cells. Potential latchup locations in the floor plan are determined, and the arrangement of at least one of the functional cells or the tap cells is modified based on the determined potential latchup locations.
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公开(公告)号：US20230014110A1
公开(公告)日：2023-01-19
申请号：US17668117
申请日：2022-02-09
发明人： Hung-Chih Ou , Wen-Hao Chen
IPC分类号： G06F30/392 , G06F30/394
摘要： A device including first track groups on a first conductive layer of an integrated circuit. Each of the first track groups including at least one of a different first track group pitch, a different first track group spacing, and a different first track group width than the other first track groups. Where each of the first track groups includes first tracks that have at least one of a different first track width and a different first track spacing than the first tracks in the other first track groups.
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