Invention Grant
- Patent Title: Channel configuration for improving multigate device performance and method of fabrication thereof
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Application No.: US17206646Application Date: 2021-03-19
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Publication No.: US11616151B2Publication Date: 2023-03-28
- Inventor: Chih-Ching Wang , Jon-Hsu Ho , Wen-Hsing Hsieh , Kuan-Lun Cheng , Zhiqiang Wu
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L29/786
- IPC: H01L29/786 ; H01L29/66 ; H01L21/8234 ; H01L29/423 ; H01L27/088 ; H01L29/06

Abstract:
Multi-gate devices and methods for fabricating such are disclosed herein. An exemplary device includes a channel layer, a first source/drain feature, a second source/drain feature, and a metal gate. The channel layer has a first horizontal segment, a second horizontal segment, and a vertical segment connects the first horizontal segment and the second horizontal segment. The first horizontal segment and the second horizontal segment extend along a first direction, and the vertical segment extends along a second direction. The vertical segment has a width along the first direction and a thickness along the second direction, and the thickness is greater than the width. The channel layer extends between the first source/drain feature and the second source/drain feature along a third direction. The metal gate wraps channel layer. In some embodiments, the first horizontal segment and the second horizontal segment are nanosheets.
Public/Granted literature
- US20210376163A1 CHANNEL CONFIGURATION FOR IMPROVING MULTIGATE DEVICE PERFORMANCE AND METHOD OF FABRICATION THEREOF Public/Granted day:2021-12-02
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