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    Air-replaced spacer for self-aligned contact scheme
    6.
    发明授权
    Air-replaced spacer for self-aligned contact scheme 有权

    公开(公告)号：US11264270B2

    公开(公告)日：2022-03-01

    申请号：US16823943

    申请日：2020-03-19

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Meng-Yu Lin ,  Chun-Fu Cheng ,  Chung-Wei Wu ,  Zhiqiang Wu

    IPC: H01L21/768 ,  H01L21/02

    Abstract: The present disclosure describes a method of fabricating a semiconductor structure that includes forming a dummy gate structure over a substrate, forming a first spacer on a sidewall of the dummy gate structure and a second spacer on the first spacer, forming a source/drain structure on the substrate, removing the second spacer, forming a dielectric structure over the source/drain structure, replacing the dummy gate structure with a metal gate structure and a capping structure on the metal gate structure, and forming an opening in the dielectric structure. The opening exposes the source/drain structure. The method further includes forming a dummy spacer on a sidewall of the opening, forming a contact structure in the opening, and removing the dummy spacer to form an air gap between the contact structure and the metal gate structure. The contact structure is in contact with the source/drain structure in the opening.

    Gate All Around Transistor Device and Fabrication Methods Thereof
    7.
    发明申请
    Gate All Around Transistor Device and Fabrication Methods Thereof 有权

    公开(公告)号：US20210343858A1

    公开(公告)日：2021-11-04

    申请号：US17170263

    申请日：2021-02-08

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chih-Ching Wang ,  Chia-Ying Su ,  Wen-Hsing Hsieh ,  Kuan-Lun Cheng ,  Chung-Wei Wu ,  Zhiqiang Wu

    IPC: H01L29/66 ,  H01L27/092 ,  H01L29/78 ,  H01L29/06 ,  H01L21/8234

    Abstract: Embodiments of the present disclosure includes a method of forming a semiconductor device. The method includes providing a substrate having a plurality of first semiconductor layers and a plurality of second semiconductor layers disposed over the substrate. The method also includes patterning the first semiconductor layers and the second semiconductor layers to form a first fin and a second fin, removing the first semiconductor layers from the first and second fins such that a first portion of the patterned second semiconductor layers becomes first suspended nanostructures in the first fin and that a second portion of the patterned second semiconductor layers becomes second suspended nanostructures in the second fin, and doping a threshold modifying impurity into the first suspended nanostructures in the first fin. The impurity causes transistors formed with the first fin and second fin have different threshold voltages.

    Channel strain inducing architecture and doping technique at replacement poly gate (RPG) stage
    8.
    发明授权
    Channel strain inducing architecture and doping technique at replacement poly gate (RPG) stage 有权

    公开(公告)号：US10861972B2

    公开(公告)日：2020-12-08

    申请号：US16390373

    申请日：2019-04-22

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Zhiqiang Wu ,  Yi-Ming Sheu ,  Tzer-Min Shen ,  Chun-Fu Cheng ,  Hong-Shen Chen

    IPC: H01L29/78 ,  H01L29/08 ,  H01L29/06 ,  H01L29/66 ,  H01L29/10 ,  H01L21/265

    Abstract: The demand for increased performance and shrinking geometry from ICs has brought the introduction of multi-gate devices including finFET devices. Inducing a higher tensile strain/stress in a region provides for enhanced electron mobility, which may improve performance. High temperature processes during device fabrication tend to relax the stress on these strain inducing layers. In some embodiments, the present disclosure relates to a finFET device and its formation. A strain-inducing layer is disposed on a semiconductor fin between a channel region and a metal gate electrode. First and second inner spacers are disposed on a top surface of the strain-inducing layer and have inner sidewalls disposed along outer sidewalls of the metal gate electrode. First and second outer spacers have innermost sidewalls disposed along outer sidewalls of the first and second inner spacers, respectively. The first and second outer spacers cover outer sidewalls of the first and second inner spacers.

    MAGNETIC MEMORY DEVICE WITH BALANCING SYNTHETIC ANTI-FERROMAGNETIC LAYER
    10.
    发明申请
    MAGNETIC MEMORY DEVICE WITH BALANCING SYNTHETIC ANTI-FERROMAGNETIC LAYER 审中-公开

    公开(公告)号：US20200005845A1

    公开(公告)日：2020-01-02

    申请号：US16395571

    申请日：2019-04-26

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Gaurav Gupta ,  Zhiqiang Wu ,  William J. Gallagher

    IPC: G11C11/16 ,  H01L43/12 ,  H01L43/10 ,  H01L43/08 ,  H01L27/22

    Abstract: In some embodiments, the present application provides a magnetic memory device. The magnetic memory device comprises a bottom electrode, and a first synthetic anti-ferromagnetic (SyAF) layer including a first pinning layer and a second pinning layer disposed over the bottom electrode and having opposite magnetization directions and separated by a first spacer layer. The magnetic memory device further comprises a reference layer disposed over the first pair of pinning layers and a free layer disposed over the reference layer and separated from the reference layer by a tunneling barrier layer. The magnetic memory device further comprises a second synthetic anti-ferromagnetic (SyAF) layer including a third pinning layer and a fourth pinning layer disposed over the free layer and having opposite magnetization directions and separated by a second spacer layer.

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