-
公开(公告)号:US20240389215A1
公开(公告)日:2024-11-21
申请号:US18787736
申请日:2024-07-29
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Tai-Yu Chen , Cho-Ying Lin , Sagar Deepak Khivsara , Hsiang Chen , Chieh Hsieh , Sheng-Kang Yu , Shang-Chieh Chien , Kai Tak Lam , Li-Jui Chen , Heng-Hsin Liu , Zhiqiang Wu
Abstract: A light source is provided capable of maintaining the temperature of a collector surface at or below a predetermined temperature. The light source in accordance with various embodiments of the present disclosure includes a processor, a droplet generator for generating a droplet to create extreme ultraviolet light, a collector for reflecting the extreme ultraviolet light into an intermediate focus point, a light generator for generating pre-pulse light and main pulse light, and a thermal image capture device for capturing a thermal image from a reflective surface of the collector.
-
公开(公告)号:US11908919B2
公开(公告)日:2024-02-20
申请号:US17200291
申请日:2021-03-12
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Chih-Ching Wang , Jon-Hsu Ho , Wen-Hsing Hsieh , Kuan-Lun Cheng , Chung-Wei Wu , Zhiqiang Wu
IPC: H01L29/66 , H01L21/8234 , H01L29/78 , H01L29/423 , H01L29/49 , H01L29/06 , H01L29/786
CPC classification number: H01L29/66484 , H01L21/823418 , H01L21/823431 , H01L29/66553 , H01L29/66795 , H01L29/7831 , H01L29/7848
Abstract: A method of manufacturing a semiconductor device includes forming a fin structure in which first semiconductor layers and second semiconductor layers are alternatively stacked; forming a sacrificial gate structure over the fin structure; etching a source/drain (S/D) region of the fin structure, which is not covered by the sacrificial gate structure, thereby forming an S/D space; laterally etching the first semiconductor layers through the S/D space, thereby forming recesses; forming a first insulating layer, in the recesses, on the etched first semiconductor layers; after the first insulating layer is formed, forming a second insulating layer, in the recesses, on the first insulating layer, wherein a dielectric constant of the second insulating layer is less than that of the first insulating layer; and forming an S/D epitaxial layer in the S/D space, wherein the second insulating layer is in contact with the S/D epitaxial layer.
-
3.
公开(公告)号:US20230327025A1
公开(公告)日:2023-10-12
申请号:US18190754
申请日:2023-03-27
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Chih-Ching Wang , Jon-Hsu Ho , Wen-Hsing Hsieh , Kuan-Lun Cheng , Zhiqiang Wu
IPC: H01L29/423 , H01L29/06 , H01L29/786 , H01L29/66 , H01L21/8234 , H01L27/088
CPC classification number: H01L29/78696 , H01L21/823412 , H01L27/088 , H01L29/0665 , H01L29/42392 , H01L29/6675 , H01L29/78645
Abstract: Multi-gate devices and methods for fabricating such are disclosed herein. An exemplary device includes a channel layer, a first source/drain feature, a second source/drain feature, and a metal gate. The channel layer has a first horizontal segment, a second horizontal segment, and a vertical segment connects the first horizontal segment and the second horizontal segment. The first horizontal segment and the second horizontal segment extend along a first direction, and the vertical segment extends along a second direction. The vertical segment has a width along the first direction and a thickness along the second direction, and the thickness is greater than the width. The channel layer extends between the first source/drain feature and the second source/drain feature along a third direction. The metal gate wraps channel layer. In some embodiments, the first horizontal segment and the second horizontal segment are nanosheets.
-
公开(公告)号:US11735594B2
公开(公告)日:2023-08-22
申请号:US17341142
申请日:2021-06-07
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Tzer-Min Shen , Zhiqiang Wu , Chung-Cheng Wu , Ching-Wei Tsai , Kuan-Lun Cheng , Chih-Hao Wang , Min Cao
IPC: H01L27/092 , H01L21/8238 , H01L29/786 , H01L27/12 , H01L21/762 , H01L21/84 , H01L29/423 , H01L29/10 , H01L29/78 , H01L29/06 , H01L29/04
CPC classification number: H01L27/1207 , H01L21/76275 , H01L21/76283 , H01L21/823807 , H01L21/823821 , H01L21/845 , H01L27/0924 , H01L27/1211 , H01L29/1033 , H01L29/42392 , H01L29/785 , H01L29/7869 , H01L21/823878 , H01L29/045 , H01L29/0673 , H01L29/7853
Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a first region and a second region; a first fin active region of a first semiconductor material disposed within the first region, oriented in a first direction, wherein the first fin active region has a crystalline direction along the first direction; and a second fin active region of a second semiconductor material disposed within the second region and oriented in the first direction, wherein the second fin active region has a crystalline direction along the first direction.
-
公开(公告)号:US11282943B2
公开(公告)日:2022-03-22
申请号:US16901881
申请日:2020-06-15
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Chih-Ching Wang , Chung-I Yang , Jon-Hsu Ho , Wen-Hsing Hsieh , Kuan-Lun Cheng , Chung-Wei Wu , Zhiqiang Wu
IPC: H01L29/66 , H01L21/8234 , H01L29/417 , H01L29/78
Abstract: The present disclosure provides a method of manufacturing a semiconductor device. The method includes forming a fin structure having first semiconductor layers and second semiconductor layers alternately stacked, forming a sacrificial gate structure over the fin structure, and etching a source/drain (S/D) region thereby forming an opening exposing at least one second semiconductor layer. The method also includes implanting an etch rate modifying species into the at least one second semiconductor layer though the opening thereby forming an implanted portion of the at least one second semiconductor layer. The method further includes selectively etching the implanted portion of the at least one second semiconductor layer, recessing end portions of the first semiconductor layers exposed in the opening, and forming an S/D epitaxial layer in the opening.
-
公开(公告)号:US11264270B2
公开(公告)日:2022-03-01
申请号:US16823943
申请日:2020-03-19
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Meng-Yu Lin , Chun-Fu Cheng , Chung-Wei Wu , Zhiqiang Wu
IPC: H01L21/768 , H01L21/02
Abstract: The present disclosure describes a method of fabricating a semiconductor structure that includes forming a dummy gate structure over a substrate, forming a first spacer on a sidewall of the dummy gate structure and a second spacer on the first spacer, forming a source/drain structure on the substrate, removing the second spacer, forming a dielectric structure over the source/drain structure, replacing the dummy gate structure with a metal gate structure and a capping structure on the metal gate structure, and forming an opening in the dielectric structure. The opening exposes the source/drain structure. The method further includes forming a dummy spacer on a sidewall of the opening, forming a contact structure in the opening, and removing the dummy spacer to form an air gap between the contact structure and the metal gate structure. The contact structure is in contact with the source/drain structure in the opening.
-
公开(公告)号:US20210343858A1
公开(公告)日:2021-11-04
申请号:US17170263
申请日:2021-02-08
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Chih-Ching Wang , Chia-Ying Su , Wen-Hsing Hsieh , Kuan-Lun Cheng , Chung-Wei Wu , Zhiqiang Wu
IPC: H01L29/66 , H01L27/092 , H01L29/78 , H01L29/06 , H01L21/8234
Abstract: Embodiments of the present disclosure includes a method of forming a semiconductor device. The method includes providing a substrate having a plurality of first semiconductor layers and a plurality of second semiconductor layers disposed over the substrate. The method also includes patterning the first semiconductor layers and the second semiconductor layers to form a first fin and a second fin, removing the first semiconductor layers from the first and second fins such that a first portion of the patterned second semiconductor layers becomes first suspended nanostructures in the first fin and that a second portion of the patterned second semiconductor layers becomes second suspended nanostructures in the second fin, and doping a threshold modifying impurity into the first suspended nanostructures in the first fin. The impurity causes transistors formed with the first fin and second fin have different threshold voltages.
-
8.
公开(公告)号:US10861972B2
公开(公告)日:2020-12-08
申请号:US16390373
申请日:2019-04-22
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Zhiqiang Wu , Yi-Ming Sheu , Tzer-Min Shen , Chun-Fu Cheng , Hong-Shen Chen
Abstract: The demand for increased performance and shrinking geometry from ICs has brought the introduction of multi-gate devices including finFET devices. Inducing a higher tensile strain/stress in a region provides for enhanced electron mobility, which may improve performance. High temperature processes during device fabrication tend to relax the stress on these strain inducing layers. In some embodiments, the present disclosure relates to a finFET device and its formation. A strain-inducing layer is disposed on a semiconductor fin between a channel region and a metal gate electrode. First and second inner spacers are disposed on a top surface of the strain-inducing layer and have inner sidewalls disposed along outer sidewalls of the metal gate electrode. First and second outer spacers have innermost sidewalls disposed along outer sidewalls of the first and second inner spacers, respectively. The first and second outer spacers cover outer sidewalls of the first and second inner spacers.
-
公开(公告)号:US10535680B2
公开(公告)日:2020-01-14
申请号:US15800390
申请日:2017-11-01
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Tzer-Min Shen , Zhiqiang Wu , Chung-Cheng Wu , Ching-Wei Tsai , Kuan-Lun Cheng , Chih-Hao Wang , Min Cao
IPC: H01L27/12 , H01L27/092 , H01L21/8238 , H01L21/762 , H01L21/84 , H01L29/423 , H01L29/786 , H01L29/78 , H01L29/04 , H01L29/06
Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a first region and a second region; a first fin active region of a first semiconductor material disposed within the first region, oriented in a first direction, wherein the first fin active region has a crystalline direction along the first direction; and a second fin active region of a second semiconductor material disposed within the second region and oriented in the first direction, wherein the second fin active region has a crystalline direction along the first direction.
-
公开(公告)号:US20200005845A1
公开(公告)日:2020-01-02
申请号:US16395571
申请日:2019-04-26
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Gaurav Gupta , Zhiqiang Wu , William J. Gallagher
Abstract: In some embodiments, the present application provides a magnetic memory device. The magnetic memory device comprises a bottom electrode, and a first synthetic anti-ferromagnetic (SyAF) layer including a first pinning layer and a second pinning layer disposed over the bottom electrode and having opposite magnetization directions and separated by a first spacer layer. The magnetic memory device further comprises a reference layer disposed over the first pair of pinning layers and a free layer disposed over the reference layer and separated from the reference layer by a tunneling barrier layer. The magnetic memory device further comprises a second synthetic anti-ferromagnetic (SyAF) layer including a third pinning layer and a fourth pinning layer disposed over the free layer and having opposite magnetization directions and separated by a second spacer layer.
-
-
-
-
-
-
-
-
-