Invention Grant
- Patent Title: Multilevel memory stack structure with tapered inter-tier joint region and methods of making thereof
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Application No.: US17098743Application Date: 2020-11-16
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Publication No.: US11621277B2Publication Date: 2023-04-04
- Inventor: Monica Titus , Zhixin Cui , Senaka Kanakamedala , Yao-Sheng Lee , Chih-Yu Lee
- Applicant: SANDISK TECHNOLOGIES LLC
- Applicant Address: US TX Addison
- Assignee: SANDISK TECHNOLOGIES LLC
- Current Assignee: SANDISK TECHNOLOGIES LLC
- Current Assignee Address: US TX Addison
- Agency: The Marbury Law Group PLLC
- Main IPC: H01L27/11582
- IPC: H01L27/11582 ; H01L27/11565 ; H01L27/11575
Abstract:
A joint level dielectric material layer is formed over a first alternating stack of first insulating layers and first spacer material layers. A first memory opening is formed with a tapered sidewall of the joint level dielectric material layer. A second alternating stack of second insulating layers and second spacer material layers is formed over the joint level dielectric material layer. An inter-tier memory opening is formed, which includes a volume of an second memory opening that extends through the second alternating stack and a volume of the first memory opening. A memory film and a semiconductor channel are formed in the inter-tier memory opening with respective tapered portions overlying the tapered sidewall of the joint level dielectric material layer.
Public/Granted literature
- US20210066347A1 MULTILEVEL MEMORY STACK STRUCTURE WITH TAPERED INTER-TIER JOINT REGION AND METHODS OF MAKING THEREOF Public/Granted day:2021-03-04
Information query
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