公开(公告)号：US20210066347A1

公开(公告)日：2021-03-04

申请号：US17098743

申请日：2020-11-16

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Monica Titus ,  Zhixin Cui ,  Senaka Kanakamedala ,  Yao-Sheng Lee ,  Chih-Yu Lee

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/11575

Abstract: A joint level dielectric material layer is formed over a first alternating stack of first insulating layers and first spacer material layers. A first memory opening is formed with a tapered sidewall of the joint level dielectric material layer. A second alternating stack of second insulating layers and second spacer material layers is formed over the joint level dielectric material layer. An inter-tier memory opening is formed, which includes a volume of an second memory opening that extends through the second alternating stack and a volume of the first memory opening. A memory film and a semiconductor channel are formed in the inter-tier memory opening with respective tapered portions overlying the tapered sidewall of the joint level dielectric material layer.

公开(公告)号：US11515250B2

公开(公告)日：2022-11-29

申请号：US17166393

申请日：2021-02-03

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Monica Titus ,  Ramy Nashed Bassely Said ,  Rahul Sharangpani ,  Senaka Kanakamedala ,  Raghuveer S. Makala

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L21/768 ,  H01L27/11582 ,  H01L27/11556

Abstract: A semiconductor structure includes at least one first semiconductor device located on a substrate, lower-level dielectric material layers embedding lower-level metal interconnect structures, at least one second semiconductor device and a dielectric material portion that overlie the lower-level dielectric material layers, at least one upper-level dielectric material layer, and an interconnection via structure vertically extending from the at least one upper-level dielectric material layer to a conductive structure that can be a node of the at least one first semiconductor device or one of lower-level metal interconnect structures. The interconnection via structure includes a transition metal layer and a fluorine-doped filler material portion in contact with the transition metal layer, composed primarily of a filler material selected from a silicide of the transition metal element or aluminum oxide, and including fluorine atoms.

公开(公告)号：US11972954B2

公开(公告)日：2024-04-30

申请号：US17355955

申请日：2021-06-23

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Roshan Jayakhar Tirukkonda ,  Senaka Kanakamedala ,  Rahul Sharangpani ,  Raghuveer S. Makala ,  Monica Titus

IPC: H01L21/311 ,  H01L21/768 ,  H01L23/535 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27 ,  H10B43/40 ,  H10B51/20 ,  H10B51/40

CPC classification number: H01L21/31144 ,  H01L21/31116 ,  H01L21/76805 ,  H01L21/76877 ,  H01L23/535 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27 ,  H10B43/40 ,  H10B51/20 ,  H10B51/40

Abstract: An alternating stack of first material layers and second material layers can be formed over a semiconductor material layer. A patterning film is formed over the alternating stack, and openings are formed through the patterning film. Via openings are formed through the alternating stack at least to a top surface of the semiconductor material layer by performing a first anisotropic etch process that transfers a pattern of the openings in the patterning film. A cladding liner can be formed on a top surface of the patterning film and sidewalls of the openings in the pattering film. The via openings can be vertically extended through the semiconductor material layer at least to a bottom surface of the semiconductor material layer by performing a second anisotropic etch process employing the cladding liner as an etch mask.

公开(公告)号：US12010841B2

公开(公告)日：2024-06-11

申请号：US17136471

申请日：2020-12-29

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Monica Titus ,  Senaka Kanakamedala ,  Rahul Sharangpani ,  Raghuveer S. Makala ,  Yao-Sheng Lee

IPC: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10

CPC classification number: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10

Abstract: An alternating stack of first material layers and second material layers is formed over a substrate. A hard mask layer is formed over the alternating stack. Optionally, an additional hard mask layer can be formed over the hard mask layer. A photoresist layer is applied and patterned, and cavities are formed in the hard mask layer by performing a first anisotropic etch process that transfers a pattern of the openings in the photoresist layer through the hard mask layer. Via openings are formed through an upper portion of the alternating stack by performing a second anisotropic etch process. A cladding liner can be optionally formed on sidewalls of the cavities in the hard mask layer. The via openings can be vertically extend through all layers within the alternating stack by performing a third anisotropic etch process.

公开(公告)号：US11621277B2

公开(公告)日：2023-04-04

申请号：US17098743

申请日：2020-11-16

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Monica Titus ,  Zhixin Cui ,  Senaka Kanakamedala ,  Yao-Sheng Lee ,  Chih-Yu Lee

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/11575

Abstract: A joint level dielectric material layer is formed over a first alternating stack of first insulating layers and first spacer material layers. A first memory opening is formed with a tapered sidewall of the joint level dielectric material layer. A second alternating stack of second insulating layers and second spacer material layers is formed over the joint level dielectric material layer. An inter-tier memory opening is formed, which includes a volume of an second memory opening that extends through the second alternating stack and a volume of the first memory opening. A memory film and a semiconductor channel are formed in the inter-tier memory opening with respective tapered portions overlying the tapered sidewall of the joint level dielectric material layer.