Invention Grant
- Patent Title: DRAM assist error correction mechanism for DDR SDRAM interface
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Application No.: US17319844Application Date: 2021-05-13
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Publication No.: US11625296B2Publication Date: 2023-04-11
- Inventor: Dimin Niu , Mu-Tien Chang , Hongzhong Zheng , Hyun-Joong Kim , Won-hyung Song , Jangseok Choi
- Applicant: Samsung Electronics Co., Ltd.
- Applicant Address: KR Suwon-si
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR Suwon-si
- Agency: Lewis Roca Rothgerber Christie LLP
- Main IPC: G06F11/00
- IPC: G06F11/00 ; G06F11/10 ; G11C5/04 ; G11C29/42 ; G11C29/52

Abstract:
A method of correcting a memory error of a dynamic random-access memory module (DRAM) using a double data rate (DDR) interface, the method includes conducting a memory transaction including multiple bursts with a memory controller to send data from data chips of the DRAM to the memory controller, detecting one or more errors using an ECC chip of the DRAM, determining a number of the bursts having the errors using the ECC chip of the DRAM, determining whether the number of the bursts having the errors is greater than a threshold number, determining a type of the errors, and directing the memory controller based on the determined type of the errors, wherein the DRAM includes a single ECC chip per memory channel.
Public/Granted literature
- US20210294697A1 DRAM ASSIST ERROR CORRECTION MECHANISM FOR DDR SDRAM INTERFACE Public/Granted day:2021-09-23
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