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    MEMORY MODULE
    2.
    发明申请
    MEMORY MODULE 有权
    记忆模块

    公开(公告)号：US20150016047A1

    公开(公告)日：2015-01-15

    申请号：US14317099

    申请日：2014-06-27

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jong-hyun Seok ,  Do-hyung Kim ,  Won-hyung Song ,  Young-ho Lee

    IPC: G06F1/18

    CPC classification number: G11C5/04 ,  G11C7/02 ,  G11C7/10 ,  G11C2207/105

    Abstract: A memory module that includes: a printed circuit board having a connecting terminal; memory chips arranged on the printed circuit board; data buffers disposed on a first surface of the printed circuit board and corresponding to the memory chips; and resistance units disposed on a second surface of the printed circuit board and corresponding to the data buffers.

    Abstract translation: 一种存储模块，包括：具有连接端子的印刷电路板; 存储芯片布置在印刷电路板上; 数据缓冲器，布置在印刷电路板的第一表面上并对应于存储器芯片; 和布置在印刷电路板的第二表面上并对应于数据缓冲器的电阻单元。

    Memory package including buffer, expansion memory module, and multi-module memory system
    6.
    发明授权
    Memory package including buffer, expansion memory module, and multi-module memory system 有权

    公开(公告)号：US10417162B2

    公开(公告)日：2019-09-17

    申请号：US15339236

    申请日：2016-10-31

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Won-hyung Song

    IPC: G06F13/40 ,  G06F1/18 ,  G06F3/06 ,  G06F13/16 ,  H01L23/00

    Abstract: Provided are a memory package, an expansion memory module, and a multi-module memory system. A base memory module, to/from which an expansion memory module is capable of being attached/detached, includes a module board, a plurality of module terminals arranged on the module board to be connected to a slot, and a plurality of memory packages, each of which including a first surface to be attached to the module board and a second surface opposite to the first surface facing away from the module board, wherein each of the plurality of memory packages includes a plurality of package terminals exposed on the second surface of the memory package to be connected to the expansion memory module.

    DRAM ASSIST ERROR CORRECTION MECHANISM FOR DDR SDRAM INTERFACE
    9.
    发明申请
    DRAM ASSIST ERROR CORRECTION MECHANISM FOR DDR SDRAM INTERFACE 有权

    公开(公告)号：US20210294697A1

    公开(公告)日：2021-09-23

    申请号：US17319844

    申请日：2021-05-13

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： DIMIN NIU ,  Mu-Tien Chang ,  Hongzhong Zheng ,  Hyun-Joong Kim ,  Won-hyung Song ,  Jangseok Choi

    IPC: G06F11/10 ,  G11C5/04 ,  G11C29/42 ,  G11C29/52

    Abstract: A method of correcting a memory error of a dynamic random-access memory module (DRAM) using a double data rate (DDR) interface, the method includes conducting a memory transaction including multiple bursts with a memory controller to send data from data chips of the DRAM to the memory controller, detecting one or more errors using an ECC chip of the DRAM, determining a number of the bursts having the errors using the ECC chip of the DRAM, determining whether the number of the bursts having the errors is greater than a threshold number, determining a type of the errors, and directing the memory controller based on the determined type of the errors, wherein the DRAM includes a single ECC chip per memory channel.

    DRAM ASSIST ERROR CORRECTION MECHANISM FOR DDR SDRAM INTERFACE
    10.
    发明申请
    DRAM ASSIST ERROR CORRECTION MECHANISM FOR DDR SDRAM INTERFACE 审中-公开

    公开(公告)号：US20190179704A1

    公开(公告)日：2019-06-13

    申请号：US16276304

    申请日：2019-02-14

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Dimin Niu ,  Mu-Tien Chang ,  Hongzhong Zheng ,  Hyun-Joong Kim ,  Won-hyung Song ,  Jangseok Choi

    IPC: G06F11/10 ,  G11C29/42 ,  G11C29/52 ,  G11C5/04

    Abstract: A method of correcting a memory error of a dynamic random-access memory module (DRAM) using a double data rate (DDR) interface, the method includes conducting a memory transaction including multiple bursts with a memory controller to send data from data chips of the DRAM to the memory controller, detecting one or more errors using an ECC chip of the DRAM, determining a number of the bursts having the errors using the ECC chip of the DRAM, determining whether the number of the bursts having the errors is greater than a threshold number, determining a type of the errors, and directing the memory controller based on the determined type of the errors, wherein the DRAM includes a single ECC chip per memory channel.

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