Invention Grant
- Patent Title: Pillar-last methods for forming semiconductor devices
-
Application No.: US17175006Application Date: 2021-02-12
-
Publication No.: US11631630B2Publication Date: 2023-04-18
- Inventor: Anilkumar Chandolu , Wayne H. Huang , Sameer S. Vadhavkar
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Perkins Coie LLP
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L23/00 ; H01L25/065 ; H01L21/683 ; H01L23/31

Abstract:
Semiconductor devices having one or more vias filled with an electrically conductive material are disclosed herein. In one embodiment, a semiconductor device includes a semiconductor substrate having a first side, a plurality of circuit elements proximate to the first side, and a second side opposite the first side. A via can extend between the first and second sides, and a conductive material in the via can extend beyond the second side of the substrate to define a projecting portion of the conductive material. The semiconductor device can have a tall conductive pillar formed over the second side and surrounding the projecting portion of the conductive material, and a short conductive pad formed over the first side and electrically coupled to the conductive material in the via.
Public/Granted literature
- US20210166996A1 PILLAR-LAST METHODS FOR FORMING SEMICONDUCTOR DEVICES Public/Granted day:2021-06-03
Information query
IPC分类: