公开(公告)号：US10957625B2

公开(公告)日：2021-03-23

申请号：US15858501

申请日：2017-12-29

Applicant: Micron Technology, Inc.

Inventor： Anilkumar Chandolu ,  Wayne H. Huang ,  Sameer S. Vadhavkar

IPC: H01L23/48 ,  H01L23/00 ,  H01L25/065 ,  H01L21/683 ,  H01L23/31

Abstract: Semiconductor devices having one or more vias filled with an electrically conductive material are disclosed herein. In one embodiment, a semiconductor device includes a semiconductor substrate having a first side, a plurality of circuit elements proximate to the first side, and a second side opposite the first side. A via can extend between the first and second sides, and a conductive material in the via can extend beyond the second side of the substrate to define a projecting portion of the conductive material. The semiconductor device can have a tall conductive pillar formed over the second side and surrounding the projecting portion of the conductive material, and a short conductive pad formed over the first side and electrically coupled to the conductive material in the via.

公开(公告)号：US20180190571A1

公开(公告)日：2018-07-05

申请号：US15910136

申请日：2018-03-02

Applicant: Micron Technology, Inc.

Inventor： Jaspreet S. Gandhi ,  Wayne H. Huang

IPC: H01L23/48 ,  H01L21/683 ,  H01L21/768 ,  H01L23/00

CPC classification number: H01L23/481 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/76898 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/02125 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/05559 ,  H01L2224/05567 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/05684 ,  H01L2224/10125 ,  H01L2224/1146 ,  H01L2224/13006 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13166 ,  H01L2224/13171 ,  H01L2224/13184 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: Semiconductor devices having a through-silicon-via and methods of forming the same are described herein. As an example, a semiconductor device may include a substrate material, a through-silicon-via protrusion extending from the substrate material, a first dielectric material formed on the substrate material, a second dielectric material formed on the first dielectric material, and an interconnect formed on the through-silicon-via protrusion, where the interconnect formed is in an opening in the second dielectric material.

公开(公告)号：US20180040592A1

公开(公告)日：2018-02-08

申请号：US15788094

申请日：2017-10-19

Applicant: Micron Technology, Inc.

Inventor： Jaspreet S. Gandhi ,  Wayne H. Huang ,  James M. Derderian

IPC: H01L25/065 ,  H01L25/075 ,  H01L23/40 ,  H01L23/00 ,  H01L25/04 ,  H01L23/498 ,  H01L23/34 ,  H01L25/00 ,  H01L23/367 ,  H01L23/42

CPC classification number: H01L25/0657 ,  H01L23/00 ,  H01L23/34 ,  H01L23/3675 ,  H01L23/4012 ,  H01L23/42 ,  H01L23/49811 ,  H01L23/49827 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/81 ,  H01L25/043 ,  H01L25/065 ,  H01L25/0756 ,  H01L25/50 ,  H01L2224/05599 ,  H01L2224/11 ,  H01L2224/13011 ,  H01L2224/13019 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16503 ,  H01L2224/73253 ,  H01L2224/81815 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01327 ,  H01L2924/05032 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012

Abstract: Interconnect structures with improved conductive properties are disclosed herein. In one embodiment, an interconnect structure can include a first conductive member coupled to a first semiconductor die and a second conductive member coupled to second semiconductor die. The first conductive member includes a recessed surface defining a depression. The second conductive member extends at least partially into the depression of the first conductive member. A bond material within the depression can at least partially encapsulate the second conductive member and thereby bond the second conductive member to the first conductive member.

公开(公告)号：US09397078B1

公开(公告)日：2016-07-19

申请号：US14635888

申请日：2015-03-02

Applicant: Micron Technology, Inc.

Inventor： Anilkumar Chandolu ,  Wayne H. Huang ,  Sameer S. Vadhavkar

IPC: H01L25/18 ,  H01L23/367 ,  H01L25/00 ,  H01L23/48 ,  H01L25/065 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L25/18 ,  H01L21/563 ,  H01L23/04 ,  H01L23/367 ,  H01L23/42 ,  H01L25/0657 ,  H01L25/50 ,  H01L29/0657 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/92125 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2225/06568 ,  H01L2225/06589 ,  H01L2924/0002 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/16235 ,  H01L2924/00

Abstract: Semiconductor device assemblies with underfill containment cavities are disclosed herein. In one embodiment, a semiconductor device assembly can include a first semiconductor die having a base region formed from a substrate material, a recessed surface along the base region, a peripheral region formed from the substrate material and projecting from the base region, and a sidewall surface along the peripheral region and defining a cavity with the sidewall surface in the peripheral region. The semiconductor device assembly further includes a thermal transfer structure attached to the peripheral region of the first die adjacent the cavity, and an underfill material at least partially filling the cavity and including a fillet between the peripheral region and the stack of second semiconductor dies.

Abstract translation: 本文公开了具有底部填充容纳腔的半导体器件组件。 在一个实施例中，半导体器件组件可以包括第一半导体管芯，其具有由基底材料形成的基极区域，沿着基底区域的凹陷表面，由基底材料形成并从底部区域突出的外围区域，以及侧壁 沿着周边区域形成表面，并且在周边区域中限定具有侧壁表面的空腔。 所述半导体器件组件还包括附接到邻近所述空腔的所述第一裸片的周边区域的热传递结构，以及至少部分地填充所述腔并且在所述外围区域和所述第二半导体管芯堆叠之间包括圆角的底部填充材料。

公开(公告)号：US10692733B2

公开(公告)日：2020-06-23

申请号：US16430814

申请日：2019-06-04

Applicant: Micron Technology, Inc.

Inventor： Jaspreet S. Gandhi ,  Wayne H. Huang

IPC: H01L21/321 ,  H01L21/768

Abstract: Systems and methods for uniform back side exposure of through-silicon vias (TSVs) are disclosed. In one embodiment, a semiconductor device comprises a substrate having a front side with circuit elements formed thereon, and a back side opposite the front side. A TSV extends between the front side and the back side of the substrate, and a dummy feature is disposed over the back side of the substrate, the dummy feature laterally spaced apart from the TSV and substantially coplanar with the TSV. In another embodiment, a semiconductor device comprises a substrate having a TSV formed therethrough, with a control material disposed over the back side of the substrate, the TSV substantially coplanar with the control material.

公开(公告)号：US20190304799A1

公开(公告)日：2019-10-03

申请号：US16430814

申请日：2019-06-04

Applicant: Micron Technology, Inc.

Inventor： Jaspreet S. Gandhi ,  Wayne H. Huang

IPC: H01L21/321 ,  H01L21/768

Abstract: Systems and methods for uniform back side exposure of through-silicon vias (TSVs) are disclosed. In one embodiment, a semiconductor device comprises a substrate having a front side with circuit elements formed thereon, and a back side opposite the front side. A TSV extends between the front side and the back side of the substrate, and a dummy feature is disposed over the back side of the substrate, the dummy feature laterally spaced apart from the TSV and substantially coplanar with the TSV. In another embodiment, a semiconductor device comprises a substrate having a TSV formed therethrough, with a control material disposed over the back side of the substrate, the TSV substantially coplanar with the control material.

公开(公告)号：US10262922B2

公开(公告)日：2019-04-16

申请号：US15910136

申请日：2018-03-02

Applicant: Micron Technology, Inc.

Inventor： Jaspreet S. Gandhi ,  Wayne H. Huang

IPC: H01L23/46 ,  H01L23/52 ,  H01L29/40 ,  H01L21/4763 ,  H01L21/44 ,  H01L23/48 ,  H01L21/768 ,  H01L23/00 ,  H01L21/683

Abstract: Semiconductor devices having a through-silicon-via and methods of forming the same are described herein. As an example, a semiconductor device may include a substrate material, a through-silicon-via protrusion extending from the substrate material, a first dielectric material formed on the substrate material, a second dielectric material formed on the first dielectric material, and an interconnect formed on the through-silicon-via protrusion, where the interconnect formed is in an opening in the second dielectric material.

公开(公告)号：US20160343689A1

公开(公告)日：2016-11-24

申请号：US15229618

申请日：2016-08-05

Applicant: Micron Technology, Inc.

Inventor： Jaspreet S. Gandhi ,  Wayne H. Huang ,  James M. Derderian

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L23/00 ,  H01L23/34 ,  H01L23/3675 ,  H01L23/4012 ,  H01L23/42 ,  H01L23/49811 ,  H01L23/49827 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/81 ,  H01L25/043 ,  H01L25/065 ,  H01L25/0756 ,  H01L25/50 ,  H01L2224/05599 ,  H01L2224/11 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16503 ,  H01L2224/73253 ,  H01L2224/81815 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01327 ,  H01L2924/05032 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012

Abstract: Interconnect structures with improved conductive properties are disclosed herein. In one embodiment, an interconnect structure can include a first conductive member coupled to a first semiconductor die and a second conductive member coupled to second semiconductor die. The first conductive member includes a recessed surface defining a depression. The second conductive member extends at least partially into the depression of the first conductive member. A bond material within the depression can at least partially encapsulate the second conductive member and thereby bond the second conductive member to the first conductive member.

公开(公告)号：US20160293519A1

公开(公告)日：2016-10-06

申请号：US14678085

申请日：2015-04-03

Applicant: Micron Technology, Inc.

Inventor： Jaspreet S. Gandhi ,  Wayne H. Huang

IPC: H01L23/48 ,  H01L21/768

CPC classification number: H01L23/481 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/76898 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/02125 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/05559 ,  H01L2224/05567 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/05684 ,  H01L2224/10125 ,  H01L2224/1146 ,  H01L2224/13006 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13166 ,  H01L2224/13171 ,  H01L2224/13184 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: Semiconductor devices having a through-silicon-via and methods of forming the same are described herein. As an example, a semiconductor device may include a substrate material, a through-silicon-via protrusion extending from the substrate material, a first dielectric material formed on the substrate material, a second dielectric material formed on the first dielectric material, and an interconnect formed on the through-silicon-via protrusion, where the interconnect formed is in an opening in the second dielectric material.

Abstract translation: 本文描述了具有穿硅通孔的半导体器件及其形成方法。 作为示例，半导体器件可以包括衬底材料，从衬底材料延伸的穿硅通孔突出部，形成在衬底材料上的第一电介质材料，形成在第一电介质材料上的第二电介质材料，以及互连 形成在穿通硅通孔突起上，其中形成的互连在第二介电材料的开口中。

公开(公告)号：US11081460B2

公开(公告)日：2021-08-03

申请号：US16236237

申请日：2018-12-28

Applicant: Micron Technology, Inc.

Inventor： Suresh Yeruva ,  Owen R. Fay ,  Sameer S. Vadhavkar ,  Adriel Jebin Jacob Jebaraj ,  Wayne H. Huang

IPC: H01L23/00

Abstract: A method of manufacturing a semiconductor device having a conductive substrate having a first surface, a second surface opposite the first surface, and a passivation material covering a portion of the first surface can include applying a seed layer of conductive material to the first surface of the conductive substrate and to the passivation material, the seed layer having a first face opposite the conductive substrate. The method can include forming a plurality of pillars comprising layers of first and second materials. The method can include etching the seed layer to undercut the seed layer between the conductive substrate and the first material of at least one of the pillars. In some embodiments, a cross-sectional area of the seed layer in contact with the passivation material between the first material and the conductive substrate is less than the cross-sectional area of the second material.