公开(公告)号：US12211746B2

公开(公告)日：2025-01-28

申请号：US17231895

申请日：2021-04-15

Applicant: Micron Technology, Inc.

Inventor： Anilkumar Chandolu ,  Indra V. Chary

IPC: H01L21/768 ,  H01L23/535 ,  H10B41/27 ,  H10B43/27

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers. Horizontally-elongated trenches are formed into the stack to form laterally-spaced memory-block regions. The memory-block regions comprise part of a memory-plane region. A pair of elevationally-extending walls are formed that are laterally-spaced relative one another and that are individually horizontally-longitudinally-elongated. The pair of walls are one of (a) or (b), where: (a): in the memory-plane region laterally-between immediately-laterally-adjacent of the memory-block regions; and (b): in a region that is edge-of-plane relative to the memory-plane region. Through the horizontally-elongated trenches and after forming the pair of walls, sacrificial material that is in the first tiers is isotropically etching away and replaced with conducting material of individual conducting lines. Other embodiments, including structure independent of method, are disclosed.

公开(公告)号：US20230017241A1

公开(公告)日：2023-01-19

申请号：US17933227

申请日：2022-09-19

Applicant: Micron Technology, Inc.

Inventor： S M Istiaque Hossain ,  Tom J. John ,  Darwin A. Clampitt ,  Anilkumar Chandolu ,  Prakash Rau Mokhna Rau ,  Christopher J. Larsen ,  Kye Hyun Baek

IPC: H01L27/11582 ,  H01L21/768

Abstract: An electronic device comprising lower and upper decks adjacent to a source. The lower and upper decks comprise tiers of alternating conductive materials and dielectric materials. Memory pillars in the lower and upper decks are configured to be operably coupled to the source. The memory pillars comprise contact plugs in the upper deck, cell films in the lower and upper decks, and fill materials in the lower and upper decks. The cell films in the upper deck are adjacent to the contact plugs and the fill materials in the upper deck are adjacent to the contact plugs. Dummy pillars are in a central region of the lower deck and the upper deck. The dummy pillars comprise an oxide material in the upper deck, the oxide material contacting the contact plugs and the fill materials. Additional electronic devices and related systems and methods are also disclosed.

公开(公告)号：US20220367512A1

公开(公告)日：2022-11-17

申请号：US17869732

申请日：2022-07-20

Applicant: Micron Technology, Inc.

Inventor： S.M. Istiaque Hossain ,  Prakash Rau Mokhna Rau ,  Arun Kumar Dhayalan ,  Damir Fazil ,  Joel D. Peterson ,  Anilkumar Chandolu ,  Albert Fayrushin ,  George Matamis ,  Christopher Larsen ,  Rokibul Islam

IPC: H01L27/11582 ,  G11C5/02 ,  H01L21/768 ,  G11C16/04 ,  G11C5/06

Abstract: Some embodiments include an integrated assembly having a first deck. The first deck has first memory cell levels alternating with first insulative levels. A second deck is over the first deck. The second deck has second memory cell levels alternating with second insulative levels. A cell-material-pillar passes through the first and second decks. Memory cells are along the first and second memory cell levels and include regions of the cell-material-pillar. An intermediate level is between the first and second decks. The intermediate level includes a buffer region adjacent the cell-material-pillar. The buffer region includes a composition different from the first and second insulative materials, and different from the first and second conductive regions. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20220310632A1

公开(公告)日：2022-09-29

申请号：US17806829

申请日：2022-06-14

Applicant: Micron Technology, Inc.

Inventor： S M Istiaque Hossain ,  Christopher J. Larsen ,  Anilkumar Chandolu ,  Wesley O. Mckinsey ,  Tom J. John ,  Arun Kumar Dhayalan ,  Prakash Rau Mokhna Rau

IPC: H01L27/1157 ,  H01L27/11578 ,  H01L27/11524 ,  H01L27/11556

Abstract: An electronic device comprising a lower deck and an upper deck adjacent to a source. Each of the lower deck and the upper deck comprise tiers of alternating conductive materials and dielectric materials. Each of the lower deck and the upper deck also comprise an array region and one or more non-array regions. Memory pillars are in the lower deck and the upper deck of the array region and the memory pillars are configured to be operably coupled to the source. Dummy pillars are in the upper deck of the one or more non-array regions and the dummy pillars are configured to be electrically isolated from the source. Another conductive material is in the upper deck and the lower deck of the one or more non-array regions. Additional electronic devices and related systems and methods of forming an electronic device are also disclosed.

公开(公告)号：US20220109002A1

公开(公告)日：2022-04-07

申请号：US17064092

申请日：2020-10-06

Applicant: Micron Technology, Inc

Inventor： Sidhartha Gupta ,  Anilkumar Chandolu ,  S M Istiaque Hossain

IPC: H01L27/11582 ,  H01L21/768 ,  G11C11/56

Abstract: An electronic device comprises a stack structure comprising vertically alternating insulative structures and conductive structures arranged in tiers, pillars extending vertically through the stack structure, and a barrier material overlying the stack structure. The electronic device comprises a first insulative material extending through the barrier material and into an upper tier portion of the stack structure, and a second insulative material laterally adjacent to the first insulative material and laterally adjacent to at least some of the conductive structures in the upper tier portion of the stack structure. At least a portion of the second insulative material is in vertical alignment with the barrier material. Additional electronic devices and related methods and systems are also disclosed.

公开(公告)号：US20220108998A1

公开(公告)日：2022-04-07

申请号：US17063101

申请日：2020-10-05

Applicant: Micron Technology, Inc.

Inventor： Anilkumar Chandolu ,  Indra V. Chary

IPC: H01L27/11556 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11582 ,  H01L27/11565 ,  H01L27/1157

Abstract: A microelectronic device includes a stack structure comprising a vertically alternating sequence of insulative structures and conductive structures arranged in tiers. At least one slit region divides the stack structure into blocks. Each block comprises an array of active pillars. Along the at least one slit region is a horizontally alternating sequence of slit structure segments and support pillar structures. The slit structure segments and the support pillar structures each extend vertically through the stack structure. Additional microelectronic devices are also disclosed as are related methods and electronic systems.

公开(公告)号：US20220068956A1

公开(公告)日：2022-03-03

申请号：US17008130

申请日：2020-08-31

Applicant: Micron Technology, Inc.

Inventor： Darwin A. Clampitt ,  Shawn D. Lyonsmith ,  Matthew J. King ,  Lisa M. Clampitt ,  John Hopkins ,  Kevin Y. Titus ,  Indra V. Chary ,  Martin Jared Barclay ,  Anilkumar Chandolu ,  Pavithra Natarajan ,  Roger W. Lindsay

IPC: H01L27/11582 ,  H01L23/528 ,  H01L23/522 ,  H01L27/11565

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a first deck located over a substrate, and a second deck located over the first deck, and pillars extending through the first and second decks. The first deck includes first memory cells, first control gates associated with the first memory cells, and first conductive paths coupled to the first control gates. The second conductive paths include second conductive pads located on a first level of the apparatus over the substrate. The second deck includes second memory cells, second control gates associated with the second memory cells, and second conductive paths coupled to the second control gates. The second conductive paths include second conductive pads located on a second level of the apparatus. The first and second conductive pads having lengths in a direction perpendicular to a direction from the first deck to the second deck.

公开(公告)号：US20220028881A1

公开(公告)日：2022-01-27

申请号：US16937303

申请日：2020-07-23

Applicant: Micron Technology, Inc.

Inventor： S M Istiaque Hossain ,  Tom J. John ,  Darwin A. Clampitt ,  Anilkumar Chandolu ,  Prakash Rau Mokhna Rau ,  Christopher J. Larsen ,  Kye Hyun Baek

IPC: H01L27/11582 ,  H01L21/768

Abstract: An electronic device comprising lower and upper decks adjacent to a source. The lower and upper decks comprise tiers of alternating conductive materials and dielectric materials. Memory pillars in the lower and upper decks are configured to be operably coupled to the source. The memory pillars comprise contact plugs in the upper deck, cell films in the lower and upper decks, and fill materials in the lower and upper decks. The cell films in the upper deck are adjacent to the contact plugs and the fill materials in the upper deck are adjacent to the contact plugs. Dummy pillars are in a central region of the lower deck and the upper deck. The dummy pillars comprise an oxide material in the upper deck, the oxide material contacting the contact plugs and the fill materials. Additional electronic devices and related systems and methods are also disclosed.

公开(公告)号：US20220005822A1

公开(公告)日：2022-01-06

申请号：US16921192

申请日：2020-07-06

Applicant: Micron Technology, Inc.

Inventor： Raja Kumar Varma Manthena ,  Anilkumar Chandolu

IPC: H01L27/11565 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582

Abstract: A method of forming a microelectronic device comprises forming a stack structure. Pillar structures are formed to vertically extend through the stack structure. At least one trench and additional trenches are formed to substantially vertically extend through the stack structure. Each of the additional trenches comprises a first portion having a first width, and a second portion at a horizontal boundary of the first portion and having a second width greater than the first width. A dielectric structure is formed within the at least one trench and the additional trenches. The dielectric structure comprises at least one angled portion proximate the horizontal boundary of the first portion of at least some of the additional trenches. The at least one angled portion extends at an acute angle to each of a first direction and a second direction transverse to the first direction. Microelectronic devices and electronic systems are also described.

公开(公告)号：US11101280B2

公开(公告)日：2021-08-24

申请号：US16728723

申请日：2019-12-27

Applicant: Micron Technology, Inc.

Inventor： Anilkumar Chandolu ,  S.M. Istiaque Hossain ,  Darwin A. Clampitt ,  Arun Kumar Dhayalan ,  Kevin R. Gast ,  Christopher Larsen ,  Prakash Rau Mokhna Rau ,  Shashank Saraf

IPC: H01L27/115 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11519 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L27/11565 ,  H01L21/311

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers comprising memory-block regions having channel-material strings therein. Conductor-material contacts are directly against the channel material of individual of the channel-material strings. First insulator material is formed directly above the conductor-material contacts. The first insulator material comprises at least one of (a) and (b), where (a): silicon, nitrogen, and one or more of carbon, oxygen, boron, and phosphorus, and (b): silicon carbide. Second insulator material is formed directly above the first insulator material and the conductor-material contacts. The second insulator material is devoid of each of the (a) and (b). Third insulator material is formed directly above the second insulator material, the first insulator material, and the conductor-material contacts. The third insulator material comprises at least one of the (a) and (b). At least one horizontally-elongated isolation structure is formed in the first and second insulator materials and in a top part of the stack in individual of the memory-block regions. Additional methods, including structure independent of method, are disclosed.