Invention Grant
- Patent Title: Epitaxial source/drain feature with enlarged lower section interfacing with backside via
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Application No.: US16901631Application Date: 2020-06-15
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Publication No.: US11631736B2Publication Date: 2023-04-18
- Inventor: Feng-Ching Chu , Wei-Yang Lee , Chia-Pin Lin
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L21/768
- IPC: H01L21/768 ; H01L29/06 ; H01L29/78 ; H01L29/66 ; H01L29/417 ; H01L29/40 ; H01L21/8234 ; H01L23/528 ; H01L27/088 ; H01L23/522

Abstract:
A semiconductor structure includes an isolation structure; first and second source/drain (S/D) features over the isolation structure, defining a first direction from the first S/D feature to the second S/D feature from a top view; one or more channel layers connecting the first and the second S/D features; a gate structure between the first and the second S/D features and engaging each of the one or more channel layers; and a via structure under the first S/D feature and electrically connecting to the first S/D feature. In a cross-sectional view perpendicular to the first direction, the via structure has a profile that widens and then narrows along a bottom-up direction.
Public/Granted literature
- US20210391421A1 Epitaxial Source/Drain Feature with Enlarged Lower Section Interfacing with Backside Via Public/Granted day:2021-12-16
Information query
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