公开(公告)号：US20240387739A1

公开(公告)日：2024-11-21

申请号：US18787148

申请日：2024-07-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Feng-Ching Chu ,  Chung-Chi Wen ,  Chia-Pin Lin

IPC: H01L29/786 ,  H01L21/02 ,  H01L29/06 ,  H01L29/161 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

Abstract: The present disclosure provides a semiconductor device and a method of forming the same. A semiconductor device according one embodiment of the present disclosure include a plurality of channel members disposed over a substrate, a plurality of inner spacer features interleaving the plurality of channel members, a gate structure wrapping around each of the plurality of channel members, and a source/drain feature. The source/drain feature includes a first epitaxial layer in contact with the substrate and the plurality of channel members, and a second epitaxial layer in contact with the first epitaxial layer and the plurality of inner spacer features. The first epitaxial layer and the second epitaxial layer include silicon germanium. A germanium content of the second epitaxial layer is greater than a germanium content of the first epitaxial layer.

公开(公告)号：US12068204B2

公开(公告)日：2024-08-20

申请号：US18359254

申请日：2023-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Feng-Ching Chu ,  Wei-Yang Lee ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC: H01L21/8238 ,  H01L27/088 ,  H01L27/092 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/66545

Abstract: A method of fabricating a fin-like field effect transistor (FinFET) device includes providing a semiconductor substrate having a region for forming p-type metal-oxide-semiconductor (PMOS) devices and a region for forming n-type metal-oxide-semiconductor (PMOS) devices, forming fin structures in both regions of the substrate separated by isolation features, first forming source/drain (S/D) features in the PMOS region, and subsequently forming S/D features in the NMOS region. First forming the PMOS S/D features and then forming the NMOS S/D features results in a greater extent of loss of isolation features in the PMOS region than in the NMOS region.

公开(公告)号：US20240251539A1

公开(公告)日：2024-07-25

申请号：US18587506

申请日：2024-02-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Feng-Ching Chu ,  Wei-Yang Lee ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC: H10B10/00 ,  H01L21/02 ,  H01L21/306 ,  H01L21/3105 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC classification number: H10B10/12 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/31053 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/42392 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/785 ,  H10B10/18

Abstract: A semiconductor device according to the present disclosure includes a gate-all-around (GAA) transistor in a first device area and a fin-type field effect transistor (FinFET) in a second device area. The GAA transistor includes a plurality of vertically stacked channel members and a first gate structure over and around the plurality of vertically stacked channel members. The FinFET includes a fin-shaped channel member and a second gate structure over the fin-shaped channel member. The fin-shaped channel member includes semiconductor layers interleaved by sacrificial layers.

公开(公告)号：US11937426B2

公开(公告)日：2024-03-19

申请号：US17246987

申请日：2021-05-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Feng-Ching Chu ,  Feng-Cheng Yang ,  Katherine H. Chiang ,  Chung-Te Lin ,  Chieh-Fang Chen

IPC: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10

CPC classification number: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10

Abstract: The present disclosure provides a semiconductor structure and a method for forming a semiconductor structure. The semiconductor structure includes a substrate, and a dielectric stack over the substrate. The dielectric stack includes a first layer over the substrate and a second layer over the first layer. The semiconductor structure further includes a gate layer including a first portion traversing the second layer and a second portion extending between the first layer and the second layer.

公开(公告)号：US11894421B2

公开(公告)日：2024-02-06

申请号：US17397728

申请日：2021-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Feng-Ching Chu ,  Wei-Yang Lee ,  Yen-Ming Chen ,  Feng-Cheng Yang

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/08 ,  H01L21/02 ,  H01L29/78 ,  H01L21/306 ,  H01L21/3065

CPC classification number: H01L29/0653 ,  H01L21/02057 ,  H01L21/02227 ,  H01L21/30604 ,  H01L29/0847 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7851 ,  H01L21/3065

Abstract: Various examples of an integrated circuit device and a method for forming the device are disclosed herein. In an example, a method includes receiving a workpiece that includes a substrate, and a device fin extending above the substrate. The device fin includes a channel region. A portion of the device fin adjacent the channel region is etched, and the etching creates a source/drain recess and forms a dielectric barrier within the source/drain recess. The workpiece is cleaned such that a bottommost portion of the dielectric barrier remains within a bottommost portion of the source/drain recess. A source/drain feature is formed within the source/drain recess such that the bottommost portion of the dielectric barrier is disposed between the source/drain feature and a remainder of the device fin.

公开(公告)号：US20220367277A1

公开(公告)日：2022-11-17

申请号：US17815302

申请日：2022-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Feng-Ching Chu ,  Wei-Yang Lee ,  Chia-Pin Lin

IPC: H01L21/8234 ,  H01L29/66 ,  H01L21/308 ,  H01L27/088 ,  H01L29/08

Abstract: A device includes a substrate, an isolation structure over the substrate, and two fins extending from the substrate and above the isolation structure. Two source/drain structures are over the two fins respectively and being side by side along a first direction generally perpendicular to a lengthwise direction of the two fins from a top view . Each of the two source/drain structures has a near-vertical side, the two near-vertical sides facing each other along the first direction. A contact etch stop layer (CESL) is disposed on at least a lower portion of the near-vertical side of each of the two source/drain structures. And two contacts are disposed over the two source/drain structures, respectively, and over the CESL.

公开(公告)号：US20220223618A1

公开(公告)日：2022-07-14

申请号：US17246987

申请日：2021-05-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Feng-Ching Chu ,  Feng-Cheng Yang ,  Katherine H. Chiang ,  Chung-Te Lin ,  Chieh-Fang Chen

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11565

Abstract: The present disclosure provides a semiconductor structure and a method for forming a semiconductor structure. The semiconductor structure includes a substrate, and a dielectric stack over the substrate. The dielectric stack includes a first layer over the substrate and a second layer over the first layer. The semiconductor structure further includes a gate layer including a first portion traversing the second layer and a second portion extending between the first layer and the second layer.

公开(公告)号：US11217490B2

公开(公告)日：2022-01-04

申请号：US16994331

申请日：2020-08-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Feng-Ching Chu ,  Wei-Yang Lee ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC: H01L21/02 ,  H01L21/8238 ,  H01L29/167 ,  H01L29/66 ,  H01L21/265 ,  H01L27/092 ,  H01L21/768 ,  H01L21/311 ,  H01L21/762 ,  H01L29/78 ,  H01L29/165 ,  H01L29/08 ,  H01L21/027 ,  H01L21/308 ,  H01L21/3115

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a substrate having a first device region and a second device region, a first fin over the substrate in the first device region, a second fin over the substrate in the second device region, a first epitaxial feature over the first fin in the source/drain region of the first fin, a second epitaxial feature over the second fin in the source/drain region of the second fin, and a dielectric layer on the first and second epitaxial features. The first epitaxial feature is doped with a first dopant of a first conductivity and the second epitaxial feature is doped with a second dopant of a second conductivity different from the first conductivity. The dielectric layer is doped with the first dopant.

公开(公告)号：US20190311957A1

公开(公告)日：2019-10-10

申请号：US16449510

申请日：2019-06-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Feng-Ching Chu ,  Wei-Yang Lee ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC: H01L21/8238 ,  H01L29/167 ,  H01L29/66 ,  H01L27/092 ,  H01L21/02 ,  H01L21/265

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a substrate having a first device region and a second device region, a first fin over the substrate in the first device region, a second fin over the substrate in the second device region, a first epitaxial feature over the first fin in the source/drain region of the first fin, a second epitaxial feature over the second fin in the source/drain region of the second fin, and a dielectric layer on the first and second epitaxial features. The first epitaxial feature is doped with a first dopant of a first conductivity and the second epitaxial feature is doped with a second dopant of a second conductivity different from the first conductivity. The dielectric layer is doped with the first dopant.

公开(公告)号：US12279451B2

公开(公告)日：2025-04-15

申请号：US17321996

申请日：2021-05-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Feng-Ching Chu ,  Chung-Chi Wen ,  Chia-Pin Lin

IPC: H01L21/02 ,  H10D30/01 ,  H10D30/67 ,  H10D30/69 ,  H10D62/00 ,  H10D62/10 ,  H10D62/832 ,  H10D64/01

Abstract: The present disclosure provides a semiconductor device and a method of forming the same. A semiconductor device according one embodiment of the present disclosure include a plurality of channel members disposed over a substrate, a plurality of inner spacer features interleaving the plurality of channel members, a gate structure wrapping around each of the plurality of channel members, and a source/drain feature. The source/drain feature includes a first epitaxial layer in contact with the substrate and the plurality of channel members, and a second epitaxial layer in contact with the first epitaxial layer and the plurality of inner spacer features. The first epitaxial layer and the second epitaxial layer include silicon germanium. A germanium content of the second epitaxial layer is greater than a germanium content of the first epitaxial layer.