Invention Grant
- Patent Title: Method for FinFET fabrication and structure thereof
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Application No.: US17362025Application Date: 2021-06-29
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Publication No.: US11646234B2Publication Date: 2023-05-09
- Inventor: Han-Yu Lin , Yi-Ruei Jhan , Fang-Wei Lee , Tze-Chung Lin , Chao-Hsien Huang , Li-Te Lin , Pinyen Lin , Akira Mineji
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
- Current Assignee Address: TW Hsinchu
- Agency: Haynes and Boone, LLP
- The original application number of the division: US16298720 2019.03.11
- Main IPC: H01L21/8234
- IPC: H01L21/8234 ; H01L27/088 ; H01L21/265 ; H01L21/764 ; H01L21/3105 ; H01L21/02 ; H01L21/311
Abstract:
A semiconductor device includes a semiconductor substrate, a semiconductor fin protruding from the semiconductor substrate, and an isolation layer disposed above the semiconductor substrate. The isolation layer includes a first portion disposed on a first sidewall of the semiconductor fin and a second portion disposed on a second sidewall of the semiconductor fin. Top surfaces of the first and second portions of the isolation layer are leveled. The first portion of the isolation layer includes an air pocket. The semiconductor device also includes a dielectric fin with a bottom portion embedded in the second portion of the isolation layer.
Public/Granted literature
- US20210327764A1 Method for FinFET Fabrication and Structure Thereof Public/Granted day:2021-10-21
Information query
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