Invention Grant
- Patent Title: Ferroelectric transistors to store multiple states of resistances for memory cells
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Application No.: US16232615Application Date: 2018-12-26
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Publication No.: US11646374B2Publication Date: 2023-05-09
- Inventor: Ashish Verma Penumatcha , Tanay Gosavi , Uygar Avci , Ian A. Young
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L29/51 ; H01L29/66 ; G11C11/22 ; H01L29/417 ; H01L21/28
Abstract:
Embodiments herein describe techniques for a semiconductor device including a gate stack with a ferroelectric-oxide layer above a channel layer and in contact with the channel layer, and a top electrode above the ferroelectric-oxide layer. The ferroelectric-oxide layer includes a domain wall between an area under a nucleation point of the top electrode and above a separation line of the channel layer between an ON state portion and an OFF state portion of the channel layer. A resistance between a source electrode and a drain electrode is modulated in a range between a first resistance value and a second resistance value, dependent on a position of the domain wall within the ferroelectric-oxide layer, a position of the ON state portion of the channel layer, and a position of the OFF state portion of the channel layer. Other embodiments may be described and/or claimed.
Public/Granted literature
- US20200212224A1 FERROELECTRIC TRANSISTORS TO STORE MULTIPLE STATES OF RESISTANCES FOR MEMORY CELLS Public/Granted day:2020-07-02
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