Invention Grant
- Patent Title: Method for polishing silicon substrate and polishing composition set
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Application No.: US16080659Application Date: 2017-02-13
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Publication No.: US11648641B2Publication Date: 2023-05-16
- Inventor: Makoto Tabata
- Applicant: FUJIMI INCORPORATED
- Applicant Address: JP Kiyosu
- Assignee: FUJIMI INCORPORATED
- Current Assignee: FUJIMI INCORPORATED
- Current Assignee Address: JP Kiyosu
- Agency: Foley & Lardner LLP
- Priority: JP 2016037247 2016.02.29
- International Application: PCT/JP2017/005139 2017.02.13
- International Announcement: WO2017/150157A 2017.09.08
- Date entered country: 2018-08-28
- Main IPC: B24B37/11
- IPC: B24B37/11 ; B24B37/00 ; H01L21/02 ; C09G1/02 ; H01L21/304 ; B24B37/08

Abstract:
Provided are a method for polishing a silicon substrate according to which PID can be reduced and a polishing composition set usable in the polishing method. The silicon substrate polishing method provided by this invention comprises a stock polishing step and a final polishing step. The stock polishing step comprises several stock polishing sub-steps carried out on one same platen. The several stock polishing sub-steps comprise a final stock polishing sub-step carried out while supplying a final stock polishing slurry PF to the silicon substrate. The total amount of the final stock polishing slurry PF supplied to the silicon substrate during the final stock polishing sub-step has a total weight of Cu and a total weight of Ni, at least one of which being 1 μg or less.
Public/Granted literature
- US20190022821A1 METHOD FOR POLISHING SILICON SUBSTRATE AND POLISHING COMPOSITION SET Public/Granted day:2019-01-24
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