Invention Grant
- Patent Title: Disaggregated die interconnection with on-silicon cavity bridge
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Application No.: US16405610Application Date: 2019-05-07
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Publication No.: US11652057B2Publication Date: 2023-05-16
- Inventor: Khang Choong Yong , Eng Huat Goh , Min Suet Lim , Robert Sankman , Telesphor Kamgaing , Wil Choon Song , Boon Ping Koh
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- Main IPC: H01L23/538
- IPC: H01L23/538 ; H01L23/31 ; H01L23/48 ; H01L25/065

Abstract:
Embodiments disclose electronic packages with a die assembly and methods of forming such electronic packages. In an embodiment, a die assembly comprises a first die and a second die laterally adjacent to the first die. In an embodiment, the first die and the second die each comprise a first semiconductor layer, an insulator layer over the first semiconductor layer, and a second semiconductor layer over the insulator layer. In an embodiment, a cavity is disposed through the second semiconductor layer. In an embodiment, the die assembly further comprises a bridge substrate that electrically couples the first die to the second die, where the bridge is positioned in the cavity of the first die and the cavity of the second die.
Information query
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