- 专利标题: Joint electron devices engineering council (JESD)204-to-peripheral component interconnect express (PCIe) interface
-
申请号: US18086773申请日: 2022-12-22
-
公开(公告)号: US11663157B1公开(公告)日: 2023-05-30
- 发明人: Gregory Uvieghara , Michael Kappes
- 申请人: IQ-Analog Corporation
- 申请人地址: US CA San Diego
- 专利权人: IQ-Analog Corporation
- 当前专利权人: IQ-Analog Corporation
- 当前专利权人地址: US CA San Diego
- 代理机构: Law Office of Gerald Maliszewski
- 代理商 Gerald Maliszewski
- 主分类号: G06F13/42
- IPC分类号: G06F13/42 ; G06F13/38
摘要:
A system and method are provided for interfacing JESD204-to-PCIe communications. The method transceives JESD204 link layer messages with a JESD204 link layer. The method converts between JESD204 link layer messages and PCIe scrambled messages. The method converts between PCIe scrambled messages and PCIe encoded messages. The PCIe encoded messages are transceived at a JESD clock rate. The PCIe encoded messages transceived at the JESD clock rate are buffered and PCIe encoded messages are then transceived at a PCIe clock rate. The PCIe encoded messages at the PCIe clock rate are transceived with a PCIe physical layer. That is, PCIe encoded messages are either transmitted to the PCIe physical layer at the PCIe clock rate (the transmission path), or received from the PCIe physical layer (at the PCIe clock rate) and buffered (the receive path). The system and method also enable conventional JESD link layer-to-JESD physical layer communications.
信息查询