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公开(公告)号：US10461764B1
公开(公告)日：2019-10-29
申请号：US16430560
申请日：2019-06-04
摘要： A system and method are provided for calibrating an interleaved digital-to-analog converter (DAC). Sets of sub-DACs are enabled, and by creating a high frequency fundamental signal, spurs can be driven down sufficiently low in frequency to be sampled and digitally converted. By minimizing the power of these digital signals, the duty cycles of the different clock phases are calibrated. Then, sets of sub-DACs are enabled and high pass filtered, so that the spurs can be downconverted using corresponding phases of the clock, to a frequency low enough to sampled and digitally converted. The power of the digital signals is minimized as a first step in phase calibration. As a final step, all the sub-DACs are enabled, the high pass filter removed, and a high frequency fundamental signal is downconverted using at least two clock phases, so that the phase difference can be measured and corrected.
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公开(公告)号：US10348263B1
公开(公告)日：2019-07-09
申请号：US16106339
申请日：2018-08-21
发明人： Kenneth Martin
摘要： A digitally controlled amplifier (DCA) has a drive (e.g., bipolar junction) transistor with a base to accept an input signal and a collector to supply an output signal. The DCA also includes n switchable gain amplifier networks (SGANs). Each SGAN has a signal input connected to the collector of the drive transistor, an input to accept a logic signal, and a signal output to supply a switchable gain AC output signal to a load in response to the logic signal. The SGAN signal outputs are connected together, typically in parallel, to supply a digitally controlled AC output gain. An auxiliary SGAN may be connected to supply a constant gain AC output signal. Each of the SGANs may have an identical switchable AC gain and accept an independent logic signal to supply (n+1) levels of digitally controlled AC output gain.
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公开(公告)号：US10291226B1
公开(公告)日：2019-05-14
申请号：US16143654
申请日：2018-09-27
发明人： Adam Vishinsky
IPC分类号： H03K5/00 , H03K17/687 , G11C27/02 , H03M1/12 , H02M1/00
摘要： A sample-and-hold circuit is presented that is current driven at the input and current sensed at the output, using two capacitors—one at the input to the ground and second past a pair of complementary CMOS switches at the output to the ground. These capacitors in connection with an input current drive form a highpass noise transfer function that substantially reduces the 1/f noise of the switches and then rolls the transfer function off, further reducing the noise. The overall noise level is significantly lower as compared to a conventional voltage-driven and voltage-sensed sample-and-hold circuit that has a lowpass transfer function which, after integration, demonstrates a noise limit of kT/C. Depending on the circuit parameters the present sample-and-hold circuit shows an integrated noise improvement of between 5 and 10 dB over kT/C limit.
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公开(公告)号：US20190013821A1
公开(公告)日：2019-01-10
申请号：US16012858
申请日：2018-06-20
摘要： A multi-zone digital-to-analog device is provided with a digital-to-analog (D/A) stage having an input to accept a digital input signal with a data bandwidth of M Hertz (Hz), a clock input to accept a clock signal with a clock frequency of P Hz, and an output to supply an analog value having a bandwidth of M Hz. An upsampling stage has an input to accept the analog value and a clock input to accept the clock signal. The upsampling stage has a device bandwidth of L Hz to supply an analog output signal with a full power bandwidth of K Hz, where (P/2)=M and M
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公开(公告)号：US09323226B1
公开(公告)日：2016-04-26
申请号：US14979186
申请日：2015-12-22
发明人： Mikko Waltari
CPC分类号： G04F10/005 , G04F10/105 , H03K4/08 , H03M1/1042 , H03M1/122 , H03M1/1295 , H03M1/14 , H03M1/361 , H03M1/56
摘要： A system and method are provided for converting voltage-to-time-to-digital signals. The method periodically samples a continuous analog input and discharges the sampled analog input at a predetermined rate to supply a continuous analog ramp signal. The ramp signal is converted into an n-bit coded digital word representing the q most significant bits (MSBs) of a k-bit binary word, where q is an integer greater than 0, n is an integer greater than 1, and k is an integer greater than q. At least one bit of the coded digital word is supplied at a time representing the p least significant bits (LSBs) of the k-bit binary word. The coded digital word is converted into a single-bit pulse signal containing timing information representing the p LSBs of the k-bit binary word at an output, and the timing information is converted into the p LSBs of the k-bit binary word.
摘要翻译： 提供了一种用于转换电压 - 时间 - 数字信号的系统和方法。 该方法周期性地采样连续的模拟输入，并以预定的速率对采样的模拟输入进行放电，以提供连续的模拟斜坡信号。 斜坡信号被转换成表示k位二进制字的q个最高有效位（MSB）的n位编码数字字，其中q是大于0的整数，n是大于1的整数，并且k是 大于q的整数。 在代表k位二进制字的p个最低有效位（LSB）的时间，提供编码数字字的至少一位。 编码数字字被转换为包含表示输出端的k位二进制字的p个LSB的定时信息的单位脉冲信号，并将定时信息转换成k位二进制字的p个LSB。
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公开(公告)号：US09178528B1
公开(公告)日：2015-11-03
申请号：US14750203
申请日：2015-06-25
发明人： Mikko Waltari
CPC分类号： G04F10/005 , H03M1/66 , H03M1/662 , H03M1/68 , H03M1/742
摘要： A current impulse (CI) method is provided for converting digital data signals to analog values. First, digital data bits are converted into current impulses. Then, the current impulses are converted into analog currents representing the digital data bits. More typically, the method accepts a k-bit digital word, and converts the k-bit digital word into (k) corresponding current impulses. In one aspect, the method accepts (n) consecutive k-bit digital words. Then, for each bit position in the k-bit digital word, (n) consecutive bits are sampled using (n) consecutive phases of an n-phase clock, creating (n) interleaved current impulses. The (n) interleaved current impulses are converted into an analog current representing the (n) consecutive k-bit digital words. Alternatively, (n) consecutive bits are sampled using (n) consecutive phases of an n-phase clock for each bit position in the k-bit digital word, creating (n) summed current impulses. A CI digital-to-analog converter is also provided.
摘要翻译： 提供了用于将数字数据信号转换为模拟值的电流脉冲（CI）方法。 首先，将数字数据位转换为当前脉冲。 然后，电流脉冲被转换为表示数字数据位的模拟电流。 更典型地，该方法接受k位数字字，并将k位数字字转换为（k）相应的当前脉冲。 一方面，该方法接受（n）个连续的k位数字字。 然后，对于k位数字字中的每个比特位置，使用n相时钟的（n）个连续相位对（n）个连续比特进行采样，创建（n）个交错的电流脉冲。 （n）交错电流脉冲被转换为表示（n）个连续k位数字字的模拟电流。 或者，使用（k）数字字中的每个位位置的n相时钟的（n）个连续相位对（n）个连续位进行采样，从而产生（n）个相加的电流脉冲。 还提供了一个CI数模转换器。
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公开(公告)号：US09098072B1
公开(公告)日：2015-08-04
申请号：US14681206
申请日：2015-04-08
发明人： Mikko Waltari
CPC分类号： G04F10/005 , H03M1/1295 , H03M1/50 , H03M1/502 , H03M1/60
摘要： A Traveling Pulse Wave Quantization method is provided for converting a time sensitive signal to a digital value. A first stop signal is delayed by a first time delay, a first plurality of times, to create a delayed first stop signal. A clock signal is delayed by a second time delay, a first plurality of times, to create a delayed clock signal first period. Each second time delay is associated with a corresponding first time delay, and the second time delay is greater than the first time delay. When the delayed first stop signal occurs before the delayed clock signal first period, a count of the delays is stopped and converted into a digital or thermometer value. An accurate resampled value is provided regardless of the duration in delay between the first stop signal and a second stop signal that is accepted after the first stop signal.
摘要翻译： 提供了一种将时间敏感信号转换为数字值的行波脉冲波量化方法。 第一停止信号被延迟第一时间延迟，第一次多次，以产生延迟的第一停止信号。 时钟信号被延迟第二时间延迟，第一次多次，以产生延迟的时钟信号第一周期。 每个第二时间延迟与对应的第一时间延迟相关联，并且第二时间延迟大于第一时间延迟。 当延迟的第一停止信号在延迟时钟信号第一周期之前发生时，延迟的计数被停止并转换成数字或温度计值。 无论第一停止信号和第一停止信号之后接受的第二停止信号的延迟持续时间如何，均提供精确的重采样值。
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8.发明授权N-path interleaving analog-to-digital converter (ADC) with background calibration 有权具有背景校准的N路交错模数转换器（ADC）公开(公告)号：US09030340B1
公开(公告)日：2015-05-12
申请号：US14531371
申请日：2014-11-03
发明人： Mikko Waltari
CPC分类号： H03M1/1245 , H03M1/0626 , H03M1/0836 , H03M1/1215
摘要： A system and method are provided of performing background corrections for an interleaving analog-to-digital converter (ADC). An analog input signal s1(t) is accepted having a first frequency f1 and a bandwidth (BW). A clock at frequency fs creates n sample clocks with evenly spaced phases, each having a sample clock frequency of fs/2. A first tone signal s2(t) is generated at second frequency f2, outside BW. The analog input signal and the first tone signal are combined, creating a combination signal, which is sampled using the sample clocks, creating n digital sample signals per clock period 1/fs. The n digital sample signals are interleaved, creating an interleaved signal. Corrections are applied that minimize errors in the interleaved signal, to obtain a corrected digital output. Errors are determined at an alias frequency f3, associated with the second frequency f2, to obtain correction information for a rotating pair of digital sample signals.
摘要翻译： 提供了一种用于对交错模数转换器（ADC）执行背景校正的系统和方法。 接受具有第一频率f1和带宽（BW）的模拟输入信号s1（t）。 频率为fs的时钟产生具有均匀间隔相位的n个采样时钟，每个时钟采样时钟频率为fs / 2。 第二音频信号s2（t）在BW外部的第二频率f2产生。 组合模拟输入信号和第一音调信号，产生一个组合信号，采用采样时钟进行采样，每个时钟周期1 / fs创建n个数字采样信号。 n个数字采样信号被交织，产生交错信号。 应用校正来最小化交错信号中的误差，以获得校正的数字输出。 以与第二频率f2相关联的别名频率f3确定错误，以获得旋转数字采样信号对的校正信息。
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公开(公告)号：US08957796B2
公开(公告)日：2015-02-17
申请号：US14507563
申请日：2014-10-06
发明人： Mikko Waltari , Michael Kappes , William Huff
CPC分类号： H03L7/091 , H03L7/093 , H03L7/097 , H03L7/18 , H03L7/1806 , H03L2207/10 , H03L2207/50 , H03M1/0626 , H03M1/0836 , H03M1/12 , H03M1/1215 , H03M1/1245
摘要： A system and method are provided for frequency multiplication jitter correction. The method accepts an analog reference signal having a first frequency, and using the analog reference signal, derives a system clock signal having a second frequency, greater than the first frequency. A PLL using a voltage controlled oscillator (VCO) is one example of a frequency multiplier. The method samples the amplitude of the analog reference signal using the system clock signal and converts the sampled analog reference signal into a digitized reference signal. In response to comparing the digitized reference signal to an ideal digitized reference signal, the phase error correction for the system clock signal is derived. The phase error correction at a first instance of time can be applied to the digitized data signal, previously converted from an analog data signal sampled at a first instance of time with the system clock signal.
摘要翻译： 提供了一种用于倍频抖动校正的系统和方法。 该方法接受具有第一频率的模拟参考信号，并且使用模拟参考信号导出具有大于第一频率的第二频率的系统时钟信号。 使用压控振荡器（VCO）的PLL是倍频器的一个例子。 该方法使用系统时钟信号对模拟参考信号的振幅进行采样，并将采样的模拟参考信号转换为数字化参考信号。 响应于将数字化参考信号与理想数字化参考信号进行比较，导出系统时钟信号的相位误差校正。 在第一时刻的相位误差校正可以应用于数字化数据信号，该数字化数据信号是先前从系统时钟信号在第一时间采样的模拟数据信号转换的。
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公开(公告)号：US20150015313A1
公开(公告)日：2015-01-15
申请号：US14503656
申请日：2014-10-01
发明人： Mikko Waltari , Michael Kappes , William Huff
CPC分类号： H03L7/091 , H03L7/093 , H03L7/097 , H03L7/18 , H03L7/1806 , H03L2207/10 , H03L2207/50 , H03M1/0626 , H03M1/0836 , H03M1/12 , H03M1/1215 , H03M1/1245
摘要： A system and method are provided for frequency multiplication jitter correction. The method accepts an analog reference signal having a first frequency, and using the analog reference signal, derives a system clock signal having a second frequency, greater than the first frequency. A PLL using a voltage controlled oscillator (VCO) is one example of a frequency multiplier. The method samples the amplitude of the analog reference signal using the system clock signal and converts the sampled analog reference signal into a digitized reference signal. In response to comparing the digitized reference signal to an ideal digitized reference signal, the phase error correction for the system clock signal is derived. The phase error correction at a first instance of time can be applied to the digitized data signal, previously converted from an analog data signal sampled at a first instance of time with the system clock signal.
摘要翻译： 提供了一种用于倍频抖动校正的系统和方法。 该方法接受具有第一频率的模拟参考信号，并且使用模拟参考信号导出具有大于第一频率的第二频率的系统时钟信号。 使用压控振荡器（VCO）的PLL是倍频器的一个例子。 该方法使用系统时钟信号对模拟参考信号的振幅进行采样，并将采样的模拟参考信号转换为数字化参考信号。 响应于将数字化参考信号与理想数字化参考信号进行比较，导出系统时钟信号的相位误差校正。 在第一时刻的相位误差校正可以应用于数字化数据信号，该数字化数据信号是先前从系统时钟信号在第一时间采样的模拟数据信号转换的。
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