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1.发明申请System and Method for Customizing Data Converters from Universal Function Dice 有权通用功能骰子定制数据转换器的系统和方法公开(公告)号：US20150061905A1
公开(公告)日：2015-03-05
申请号：US14537587
申请日：2014-11-10
发明人： Michael Kappes
CPC分类号： H03M1/1071 , H03M1/005 , H03M1/12 , H03M1/66
摘要： A method is provided for supplying a customized data converter fabricated from a universal function die. The method initially fabricates a plurality of universal data converter dice. Each universal data converter die is capable of performing a first plurality of data conversion algorithms. After the dice are made, each universal data converter die is tested to verify the performance of the first plurality of data conversion algorithms. Subsequently, a request is received for a customized data converter capable of performing a first data conversion function, which is selected from among the first plurality of data conversion algorithms. The method then fabricates a customized data converter capable of performing the first data conversion function, using a tested universal data converter die. The unselected data converter functions are disabled (not enabled). A configuration interface may be used to enable the requested data conversion function.
摘要翻译： 提供了一种用于提供由通用功能模具制造的定制数据转换器的方法。 该方法最初制造了多个通用数据转换器骰子。 每个通用数据转换器管芯能够执行第一多个数据转换算法。 在制作骰子之后，测试每个通用数据转换器管芯以验证第一多个数据转换算法的性能。 随后，对于能够执行从第一多个数据转换算法中选择的第一数据转换功能的定制数据转换器，接收到请求。 然后，该方法使用测试的通用数据转换器芯片制造能够执行第一数据转换功能的定制数据转换器。 未选择的数据转换器功能被禁用（未启用）。 可以使用配置接口来启用所请求的数据转换功能。
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公开(公告)号：US11663157B1
公开(公告)日：2023-05-30
申请号：US18086773
申请日：2022-12-22
发明人： Gregory Uvieghara , Michael Kappes
CPC分类号： G06F13/4291 , G06F13/387 , G06F2213/0026
摘要： A system and method are provided for interfacing JESD204-to-PCIe communications. The method transceives JESD204 link layer messages with a JESD204 link layer. The method converts between JESD204 link layer messages and PCIe scrambled messages. The method converts between PCIe scrambled messages and PCIe encoded messages. The PCIe encoded messages are transceived at a JESD clock rate. The PCIe encoded messages transceived at the JESD clock rate are buffered and PCIe encoded messages are then transceived at a PCIe clock rate. The PCIe encoded messages at the PCIe clock rate are transceived with a PCIe physical layer. That is, PCIe encoded messages are either transmitted to the PCIe physical layer at the PCIe clock rate (the transmission path), or received from the PCIe physical layer (at the PCIe clock rate) and buffered (the receive path). The system and method also enable conventional JESD link layer-to-JESD physical layer communications.
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公开(公告)号：US10110409B1
公开(公告)日：2018-10-23
申请号：US15964186
申请日：2018-04-27
摘要： A multi-zone analog-to-digital converter (ADC) is provided that includes a track-and-hold (T/H) stage having a bandwidth of L Hertz (Hz) to accept an analog input signal, a clock input to accept a clock signal with a clock frequency of P Hz, and N deinterleaved signal outputs with a combined bandwidth of M Hz. N×(P/2)=M, L>Q×M, and Q is an integer >1. The T/H stage is able to sample an analog input signal in the Qth Nyquist Zone, where Q is an integer. A quantizer stage has N interleaved signal inputs connected to corresponding T/H stage signal outputs, a clock input to accept the clock signal, and an output to supply a digital output signal having a bandwidth of M Hz. A packaging interface typically connects the T/H stage to the quantizer stage, and has a bandwidth less than the clock frequency.
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公开(公告)号：US08917124B1
公开(公告)日：2014-12-23
申请号：US14503656
申请日：2014-10-01
发明人： Mikko Waltari , Michael Kappes , William Huff
CPC分类号： H03L7/091 , H03L7/093 , H03L7/097 , H03L7/18 , H03L7/1806 , H03L2207/10 , H03L2207/50 , H03M1/0626 , H03M1/0836 , H03M1/12 , H03M1/1215 , H03M1/1245
摘要： A system and method are provided for frequency multiplication jitter correction. The method accepts an analog reference signal having a first frequency, and using the analog reference signal, derives a system clock signal having a second frequency, greater than the first frequency. A PLL using a voltage controlled oscillator (VCO) is one example of a frequency multiplier. The method samples the amplitude of the analog reference signal using the system clock signal and converts the sampled analog reference signal into a digitized reference signal. In response to comparing the digitized reference signal to an ideal digitized reference signal, the phase error correction for the system clock signal is derived. The phase error correction at a first instance of time can be applied to the digitized data signal, previously converted from an analog data signal sampled at a first instance of time with the system clock signal.
摘要翻译： 提供了一种用于倍频抖动校正的系统和方法。 该方法接受具有第一频率的模拟参考信号，并且使用模拟参考信号导出具有大于第一频率的第二频率的系统时钟信号。 使用压控振荡器（VCO）的PLL是倍频器的一个例子。 该方法使用系统时钟信号对模拟参考信号的振幅进行采样，并将采样的模拟参考信号转换为数字化参考信号。 响应于将数字化参考信号与理想数字化参考信号进行比较，导出系统时钟信号的相位误差校正。 在第一时刻的相位误差校正可以应用于数字化数据信号，该数字化数据信号是先前从系统时钟信号在第一时刻采样的模拟数据信号转换的。
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公开(公告)号：US20190013821A1
公开(公告)日：2019-01-10
申请号：US16012858
申请日：2018-06-20
摘要： A multi-zone digital-to-analog device is provided with a digital-to-analog (D/A) stage having an input to accept a digital input signal with a data bandwidth of M Hertz (Hz), a clock input to accept a clock signal with a clock frequency of P Hz, and an output to supply an analog value having a bandwidth of M Hz. An upsampling stage has an input to accept the analog value and a clock input to accept the clock signal. The upsampling stage has a device bandwidth of L Hz to supply an analog output signal with a full power bandwidth of K Hz, where (P/2)=M and M
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公开(公告)号：US08957796B2
公开(公告)日：2015-02-17
申请号：US14507563
申请日：2014-10-06
发明人： Mikko Waltari , Michael Kappes , William Huff
CPC分类号： H03L7/091 , H03L7/093 , H03L7/097 , H03L7/18 , H03L7/1806 , H03L2207/10 , H03L2207/50 , H03M1/0626 , H03M1/0836 , H03M1/12 , H03M1/1215 , H03M1/1245
摘要： A system and method are provided for frequency multiplication jitter correction. The method accepts an analog reference signal having a first frequency, and using the analog reference signal, derives a system clock signal having a second frequency, greater than the first frequency. A PLL using a voltage controlled oscillator (VCO) is one example of a frequency multiplier. The method samples the amplitude of the analog reference signal using the system clock signal and converts the sampled analog reference signal into a digitized reference signal. In response to comparing the digitized reference signal to an ideal digitized reference signal, the phase error correction for the system clock signal is derived. The phase error correction at a first instance of time can be applied to the digitized data signal, previously converted from an analog data signal sampled at a first instance of time with the system clock signal.
摘要翻译： 提供了一种用于倍频抖动校正的系统和方法。 该方法接受具有第一频率的模拟参考信号，并且使用模拟参考信号导出具有大于第一频率的第二频率的系统时钟信号。 使用压控振荡器（VCO）的PLL是倍频器的一个例子。 该方法使用系统时钟信号对模拟参考信号的振幅进行采样，并将采样的模拟参考信号转换为数字化参考信号。 响应于将数字化参考信号与理想数字化参考信号进行比较，导出系统时钟信号的相位误差校正。 在第一时刻的相位误差校正可以应用于数字化数据信号，该数字化数据信号是先前从系统时钟信号在第一时间采样的模拟数据信号转换的。
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公开(公告)号：US20150015313A1
公开(公告)日：2015-01-15
申请号：US14503656
申请日：2014-10-01
发明人： Mikko Waltari , Michael Kappes , William Huff
CPC分类号： H03L7/091 , H03L7/093 , H03L7/097 , H03L7/18 , H03L7/1806 , H03L2207/10 , H03L2207/50 , H03M1/0626 , H03M1/0836 , H03M1/12 , H03M1/1215 , H03M1/1245
摘要： A system and method are provided for frequency multiplication jitter correction. The method accepts an analog reference signal having a first frequency, and using the analog reference signal, derives a system clock signal having a second frequency, greater than the first frequency. A PLL using a voltage controlled oscillator (VCO) is one example of a frequency multiplier. The method samples the amplitude of the analog reference signal using the system clock signal and converts the sampled analog reference signal into a digitized reference signal. In response to comparing the digitized reference signal to an ideal digitized reference signal, the phase error correction for the system clock signal is derived. The phase error correction at a first instance of time can be applied to the digitized data signal, previously converted from an analog data signal sampled at a first instance of time with the system clock signal.
摘要翻译： 提供了一种用于倍频抖动校正的系统和方法。 该方法接受具有第一频率的模拟参考信号，并且使用模拟参考信号导出具有大于第一频率的第二频率的系统时钟信号。 使用压控振荡器（VCO）的PLL是倍频器的一个例子。 该方法使用系统时钟信号对模拟参考信号的振幅进行采样，并将采样的模拟参考信号转换为数字化参考信号。 响应于将数字化参考信号与理想数字化参考信号进行比较，导出系统时钟信号的相位误差校正。 在第一时刻的相位误差校正可以应用于数字化数据信号，该数字化数据信号是先前从系统时钟信号在第一时间采样的模拟数据信号转换的。
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公开(公告)号：US10033398B1
公开(公告)日：2018-07-24
申请号：US15787298
申请日：2017-10-18
摘要： A multi-zone digital-to-analog device is provided with a digital-to-analog (D/A) stage having an input to accept a digital input signal with a data bandwidth of M Hertz (Hz), a clock input to accept a clock signal with a clock frequency of P Hz, and an output to supply an analog value having a bandwidth of M Hz. An upsampling stage has an input to accept the analog value and a clock input to accept the clock signal. The upsampling stage has a device bandwidth of L Hz to supply an analog output signal with a full power bandwidth of K Hz, where (P/2)=M and M
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公开(公告)号：US09979582B1
公开(公告)日：2018-05-22
申请号：US15673228
申请日：2017-08-09
CPC分类号： H04L27/2666 , H03M1/06 , H03M1/121 , H03M3/496 , H04B2001/0491 , H04L5/0008 , H04L27/2092 , H04L2027/0081
摘要： A multi-zone analog-to-digital converter (ADC) is provided that includes a track-and-hold (T/H) stage having a bandwidth of L Hertz (Hz) to accept an analog input signal, a clock input to accept a clock signal with a clock frequency of P Hz, and N deinterleaved signal outputs with a combined bandwidth of M Hz. N×(P/2)=M, L>Q×M, and Q is an integer >1. The T/H stage is able to sample an analog input signal in the Qth Nyquist Zone, where Q is an integer. A quantizer stage has N interleaved signal inputs connected to corresponding T/H stage signal outputs, a clock input to accept the clock signal, and an output to supply a digital output signal having a bandwidth of M Hz. A packaging interface typically connects the T/H stage to the quantizer stage, and has a bandwidth less than the clock frequency.
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公开(公告)号：US09258004B2
公开(公告)日：2016-02-09
申请号：US14656880
申请日：2015-03-13
发明人： Michael Kappes
CPC分类号： H03M1/1071 , H03M1/005 , H03M1/12 , H03M1/66
摘要： A method is provided for supplying a customized data converter fabricated from a universal function die. The method initially fabricates a plurality of universal data converter dice. Each universal data converter die is capable of performing a first plurality of data conversion algorithms. After the dice are made, each universal data converter die is tested to verify the performance of the first plurality of data conversion algorithms. Subsequently, a request is received for a customized data converter capable of performing a first data conversion function, which is selected from among the first plurality of data conversion algorithms. The method then fabricates a customized data converter capable of performing the first data conversion function, using a tested universal data converter die. The unselected data converter functions are disabled (not enabled). A configuration interface may be used to enable the requested data conversion function.
摘要翻译： 提供了一种用于提供由通用功能模具制造的定制数据转换器的方法。 该方法最初制造了多个通用数据转换器骰子。 每个通用数据转换器管芯能够执行第一多个数据转换算法。 在制作骰子之后，测试每个通用数据转换器管芯以验证第一多个数据转换算法的性能。 随后，对于能够执行从第一多个数据转换算法中选择的第一数据转换功能的定制数据转换器，接收到请求。 然后，该方法使用测试的通用数据转换器芯片制造能够执行第一数据转换功能的定制数据转换器。 未选择的数据转换器功能被禁用（未启用）。 可以使用配置接口来启用所请求的数据转换功能。
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